A Fault Tolerant Interconnection Network for Memory-Coupled Multiprocessor Systems

  • U. Hildebrand
Part of the Informatik-Fachberichte book series (INFORMATIK, volume 283)


In this paper a concept for mapping a logical torus topology onto a physical interconnection structure will be presented. This kind of realization will obtain a reduction of the number of necessary communication paths by using additional dynamic network components. Therefore the hardware complexity for the interconnection network of a memory-coupled multiprocessor system can be reduced. The employment of such network components will yield additional aspects of fault tolerance given by the structure of the network component itself and the interconnection structure of the multiprocessor system which results when such network components are used. The primary subject of this paper will be the mechanisms of the interconnection network provided at hardware level. Therefore these mechanisms can be utilized time efficiently by the user or the operating system for instance for fault tolerance purposes.


Memory Access Fault Tolerance Interconnection Network Stable Storage Access Pattern 
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  1. [AMD 88]
    Advanced Micro Devices: Am29C982/29C983 Multiple Bus Exchange Handbook, Sunnyvale, Cal., 1988Google Scholar
  2. [BEL 86]
    Belli, F.; Echtle, K.; Görke, W.: Methoden und Modelle der Fehlertoleranz, Informatik Spektrum, Themenheft „Fehlertoleranz in Systemen“, Band 9, Heft 2, Aprill986, S. 68–81Google Scholar
  3. [DAL 89]
    Dal Cin, M.; Hildebrand, U.; Hohl, W.; Lehmann, L.; Michel, E.: Mechanismen zur Fehlerdiagnose und -behebung für die MEMS Y-Hochleistungsstruktur, Arbeitsberichte des IMMD, Band 22, Nr. 13, Erlangen, 1989, S. 113–130Google Scholar
  4. [FRI 89]
    Fritsch, G. et al.: Distributed Shared Memory Architecture MEMSY for High Performance Parallel Computations, Computer Architecture News, Dec. 1989[HÄN85]Google Scholar
  5. [Hän 85]
    Händler, W. et al.: A Tightly Coupled Hierarchical Multiprocessor Architecture, Computer Physics Comm. 37, 1985, pp. 87–93CrossRefGoogle Scholar
  6. [H3L90]
    Hildebrand, U.: Verbindungs-Hardware für ein modular erweiterbares Multiprozessorsystem mit verteiltem gemeinsamen Speicher, Gl/PARS-Mitteilungen, Nr. 7, Erlangen, Feb. 1990, S. 96 -105Google Scholar
  7. [LAM81]
    Lampson, B. W.: Atomic Transactions, in Distributed Systems - Architecture and Implementation, Lecture Notes in Computer Science 105, Springer, Berlin, 1981, pp. 246–265Google Scholar
  8. [LEE 90]
    Lee, P. A.; Anderson, L.: Fault Tolerance - Principles and Practice, Dependable Computing and Fault-Tolerant Systems Vol. 3, Springer, Wien, 1990, S. 180 ffGoogle Scholar
  9. [LEH90]
    Lehmann-Emilius, L.: Rekonfiguration und Rückwärtsfehlerbehebung für Multiprozessoren mit begrenzter Nachbarschaft, Dissertation, Arbeitsberichte des IMMD, Band 23, Nr. 2, Erlangen, 1990, S. 47 ffGoogle Scholar
  10. [MAE 86]
    Maetile, E.; Moritzen, K.; Wirl, K.: Fault-Tolerant Hardware Configuration Management on the Multiprocessor DIRMU 25, Proc. CONPAR 86, Springer Lecture Notes on Computer Science 237, 1986, S. 190–197Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1991

Authors and Affiliations

  • U. Hildebrand
    • 1
  1. 1.IMMD III, University of Erlangen - NurembergErlangenGermany

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