Stress-Induced Defects vs Growth Faults in CVD-Grown SiC

Abstract

β-SiC grown on Si by CVD contains a large density of line defects as well as planar defects. The line defects are the misfit dislocations which are located at the SiC/Si interface, as well as threading dislocations which propagate through the epilayer initiating from the Si/SiC interface an terminating at the SiC/gas interface, or at an IDB, or even back at the SiC/Si interface. Planar defects consist of twins, stacking faults and, in the case of on-axis growth, inversion domain boundaries (IDBs). In the latter case, and when an IDB is facetted, there is also a third type of dislocation at the intersection of facets herein called “IDB dislocations”. In this paper, the mecjianism of formation of these defects is discussed. It will be argued that the misfit and threading dislocations are generated by the mismatch stresses (lattice and/or thermal) while twins and stacking faults are growth defects formed by deposition errors in the early stages of the growth. It will also be shown-that the IDB dislocations are a crystallographic consequence of facetting. Experimental evidence is presented which supports the model developed for the formation of planar faults.