Advertisement

Design Overview

  • Michael Faix

Abstract

The Capitol chip set is a high-performance multi-chip 32-bit microprocessor implementing the System/370 mainframe architecture as described in System/370 Principles of Operation [IBM1]. The implementation uses some structural elements of two predecessor machines, the IBM 4361 and the IBM 9370–90 processors, both realized in high speed bipolar technology. Especially the same microinstruction format is used. The Capitol chip set realization uses a set of 12.7 mm chips in a 1.0μm. CMOS technology with a high-density master image that contains logic and RAMs. Three layers of metal are used, two for wiring and one for power distribution and I/O redistribution for the central-area pad arrangement. Other chips with a more standard CMOS technology complement the chip set.

Keywords

Cache Line Logic Design Main Store Virtual Address Control Store 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • Michael Faix

There are no affiliations available

Personalised recommendations