The design of the Capitol chip set used a new hardware design language, in the following referred to as Design Language. It is a structural language that was designed to serve as an input medium for both logic simulation and synthesis. The corresponding compiler generates simulation code for the Boeblingen Mixed Level Design Verification Simulator (see “3.7 Logic Simulation” on page 190) and input for IBM’s Logic Synthesis System (LSS) [DAR2].
KeywordsDesign Level Combinational Logic Logic Synthesis Boolean Equation Logic Simulation
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