Abstract
Compiled graph reduction has proven successful for the sequential implementation of functional programming languages. In order to use this method for parallel evaluation we developed a parallel abstract machine for the implementation of functional languages on a processor network. It is based on Th. Johnssons G-machine [Johnsson], an abstract machine performing compiled graph reduction.
We first present some ideas concerning the modification of the sequential G -machine in order to reduce the overhead of the reduction. Then we give a summary of the parallel machine and discuss some aspects of its realization, especially what kind of communication and work distribution will be used.
Work supported by the Deutsche Forschungsgemeinschaft in the SFB 124 — VLSI-Design and Parallelism
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© 1988 Springer-Verlag Berlin Heidelberg
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Raber, M. et al. (1988). Compiled Graph Reduction on a Processor Network. In: Kastens, U., Rammig, F.J. (eds) Architektur und Betrieb von Rechensystemen. Informatik-Fachberichte, vol 168. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-73451-9_16
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DOI: https://doi.org/10.1007/978-3-642-73451-9_16
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