Abstract
As a consequence of studies concerning a fault-tolerant microprogrammed microprocessor an error-detection and error-correction scheme for logical operations has been developed. Implementing inverse residue coding for error-detection and inverse biresidue coding for error-correction the hardware is considered. The theoretical basis of residue coding is briefly summarized and the error-detection/error-correction of logical operations is presented. Concurrent error-detection capability is discussed as well as the estimation of hardware overhead.
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© 1984 Springer-Verlag Berlin Heidelberg
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Trautwein, W.M. (1984). Concurrent Error-Detection/-Correction of Logical Operations. In: Großpietsch, KE., Dal Cin, M. (eds) Fehlertolerierende Rechensysteme. Informatik-Fachberichte, vol 84. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-69698-5_16
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DOI: https://doi.org/10.1007/978-3-642-69698-5_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-13348-3
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