Abstract
MIPS (Microprocessor without Interlocked Pipe Stages) is a general purpose processor architecture designed to be implemented on a single VLSI chip. The main goal of the design is high performance in the execution of compiled code. The architecture is experimental since it is a radical break with the trend of modern computer architectures. The basic philosophy of MIPS is to present an instruction set that is a compiler-driven encoding of the microengine. Thus, little or no decoding is needed and the instructions correspond closely to microcode instructions. The processor is pipelined but provides no pipeline interlock hardware; this function must be provided by software.
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© 1981 Carnegie-Mellon University
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Hennessy, J., Jouppi, N., Baskett, F., Gill, J. (1981). MIPS: A VLSI Processor Architecture. In: Kung, H.T., Sproull, B., Steele, G. (eds) VLSI Systems and Computations. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-68402-9_37
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DOI: https://doi.org/10.1007/978-3-642-68402-9_37
Publisher Name: Springer, Berlin, Heidelberg
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