VLSI Implementations of a Reduced Instruction Set Computer

  • Daniel T. Fitzpatrick
  • Manolis G. H. Katevenis
  • David A. Patterson
  • Zvi Peshkess
  • Robert W. Sherburne
  • John K. Foderaro
  • Howard A. Landman
  • James B. Peek
  • Carlo H. Séquin
  • Korbin S. Van Dyke

Abstract

A general trend in computers today is to increase the complexity of architectures commensurate with the increasing potential of implementation technologies. Consequences of this complexity are increased design time, more design errors, inconsistent implementations, and the delay of single chip implementation[7]. The Reduced Instruction Set Computer (RISC) Project investigates a VLSI alternative to this trend. Our initial design is called RISC I.

References

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Copyright information

© Carnegie-Mellon University 1981

Authors and Affiliations

  • Daniel T. Fitzpatrick
    • 1
  • Manolis G. H. Katevenis
    • 1
  • David A. Patterson
    • 1
  • Zvi Peshkess
    • 1
  • Robert W. Sherburne
    • 1
  • John K. Foderaro
    • 1
  • Howard A. Landman
    • 1
  • James B. Peek
    • 1
  • Carlo H. Séquin
    • 1
  • Korbin S. Van Dyke
    • 1
  1. 1.Computer Science Division/EECS DepartmentUniversity of California at BerkeleyBerkeleyUSA

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