Abstract
This paper introduces a new technique, called syntax-directed verification, for proving properties of circuits composed of standard cells. The lengths of proofs using this technique are independent of the size of the circuits, but depend only on the number of standard cell types and the complexity of the rules for interconnecting them. Syntax-directed verification is thus well-suited to VLSI, in which large circuits are built using relatively few types of cells. The paper describes the syntax-directed verification method, and presents an example of its use.
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References
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© 1981 Carnegie-Mellon University
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Foster, M.J. (1981). Syntax-Directed Verification of Circuit Function. In: Kung, H.T., Sproull, B., Steele, G. (eds) VLSI Systems and Computations. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-68402-9_22
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DOI: https://doi.org/10.1007/978-3-642-68402-9_22
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-68404-3
Online ISBN: 978-3-642-68402-9
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