Pipeline of the Coarse Structure Model

  • Ulrich Golze


The RISC processor TOOBSIE was externally specified in Chapter 5 by a simulatable HDL behavior model. This golden device defines the instruction semantics. To implement this behavior, an internal architecture with a time behavior was specified in Chapter 6. Although these specifications were rather detailed and contained important design decisions, we have not yet proved that the specified parts fit together and do really generate the reference behavior.


Memory Access Register File Pipeline Stage System Clock Instruction Register 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • Ulrich Golze
    • 1
  1. 1.Department of Integrated Circuit Design (E.I.S.)Technical University of BraunschweigBraunschweigGermany

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