Internal Specification of Coarse Structure
- 197 Downloads
In the previous chapter, the RISC processor TOOBSIE was specified externally by defining its “outside” behavior, basically its instruction syntax and semantics, as seen by an application programmer. For reference purposes, the Interpreter Model was developed as a golden device in the HDL VERILOG.
KeywordsMemory Access Register File Pipeline Stage Internal Specification Coarse Structure
Unable to display preview. Download preview PDF.