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Partitioning Strategies in Circuit Simulation

  • M. Günther
  • M. Hoschek
Part of the Lecture Notes in Computational Science and Engineering book series (LNCSE, volume 8)

Abstract

Partitioning strategies are commonly used in network analysis packages for simulating highly integrated circuits such as dynamic memories. These methods allow chip designers to simulate circuits consisting of millions of transistors in reasonable computation time. Using a standard benchmark example, the inverter chain, we consider different approaches used in network analysis to split the system on circuit level. We will show the connection with split numerical methods for ordinary differential equations with partitioned right-hand sides.

Keywords

Circuit Simulation Partitioning Strategy Circuit Level Stiff Method Waveform Relaxation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • M. Günther
    • 1
  • M. Hoschek
    • 1
  1. 1.Fachbereich MathematikTechnische Universität DarmstadtDarmstadtGermany

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