VHDL Specification of a FPGA to Divide and Multiply in GF(2m)

  • Mario Alberto García-Martínez
  • Guillermo Morales-Luna


Some FPGA’s are designed to compute division and multiplication on Galois fields. FPGA’s are quite cheap programmable logic devices used in digital circuits with the important characteristic of being reprogrammable. Any FPGA can be specified within VHDL which at present is a standard language in the design of digital systems. We describe in VHDL the divider and multiplier basic cells and their whole integration. The structures have scalable systolic architectures. The circuits operate by pipelining; the divider in GF (2 m ) requires 5m − 1 clock cycles while the multiplier 3m − 1. The divider proceeds by the Gaussian triangulation algorithm and is uniform with respect to the irreducible polynomial generating the field. The codes, some simulations and performance measurements are provided.


Clock Cycle Field Programmable Gate Array Finite Field Systolic Array Irreducible Polynomial 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Araki K., Fujita I. and Morisue M. “Fast inverter over finite fields based on Euclid’s algorithm”, Trans. I.ICE, vol. E-72, pp. 1230–1234, Nov. 1989Google Scholar
  2. 2.
    Chin L.W. “New Systolic Arrays for C AB2, Inversion and Division in GF(2m)”. IEEE Trans. on Comp. vol. 49, nr.10, pp. 1120–1125, Oct, 2000MathSciNetCrossRefGoogle Scholar
  3. 3.
    Dewey A. M. Analysis and Design of Digital Systems with VHDL. PWS Publishing Company, 1997Google Scholar
  4. 4.
    Fenn S. T. J., Benessia M. and Taylor D., “GF(2m) Multiplication and Division Over the Dual Basis”, IEEE Trans. on Comp., vol. 45, nr. 3, pp. 319–327, Mar. 1996.zbMATHCrossRefGoogle Scholar
  5. 5.
    Garcia Martinez M. A. “Procesador de Division para Campos de Galois en un PLD”. Tesis de Maestria, Inst. Tec. de Orizaba, 1999Google Scholar
  6. 6.
    Hasan M. A. and Bhargava V. K. “Bit Serial systolic Divider and Multiplier for Finite Fields GF(2m)”. IEEE Trans. Comp., vol. 41, nr. 8, pp. 972–979, Aug. 1992MathSciNetCrossRefGoogle Scholar
  7. 7.
    Hsu Y.-C., Tsai K. F., Liu J. T. and Lin E. S. VHDL Modeling for Digital Design Synthesis. Kluwer Academic Publishers, 1995zbMATHGoogle Scholar
  8. 8.
    Lee K.-J. and Yoo K.-Y. “Linear systolic multiplier/squarer for fast exponentiation”. Inf. Proc. Letters, vol. 76, pp. 105–111, 2000.MathSciNetCrossRefGoogle Scholar
  9. 9.
    Peterson W. W. and Weldon E. J. Error Correcting Codes. MIT, Cambridge, Massachusetts, 1972zbMATHGoogle Scholar
  10. 10.
    Sunar B. and Koç C.K. “Mastrovito Multiplier for All Trinomials”. IEEE Trans. on Comp. vol. 48, nr. 5, pp. 522–527, May. 1999.CrossRefGoogle Scholar
  11. 11.
    Xilinx. Foundation Series 2.1i Quick Start Guide. Foundation Series Software from Xilinx. 1999Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Mario Alberto García-Martínez
    • 1
  • Guillermo Morales-Luna
    • 2
    • 3
  1. 1.Departamento de Ingeniería Eléctrica-ElectrónicaInstituto Tecnológico de OrizabaOrizaba, VeracruzMexico
  2. 2.Programa de Ingeniería MolecularInstituto Mexicano del PetróleoMexico
  3. 3.Computer Science SectionMexico D.F.Mexico

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