CISC Processors

Abstract

Modern superscalar processors, which will be covered extensively in Chap. 4, use multiple FUs. To keep these FUs as busy as possible situations must be allowed where instructions are executed in a different order from that of the original program. Techniques supporting such an out-of-order execution were developed even in the mid-1960s in some complex instruction set computers (CISC) which were large mainframe computers at that time. It would take too much space to describe CISC mainframes in detail. Therefore we only briefly itemize some in this chapter and point out those that made a strong impact on the microarchitecture of today’s superscalars.

Out-of-order execution is not a new concept — it existed twenty years ago on [CISC] IBM and CDC computers — but it is innovative for single-chip implementations…

Mark Brehob, Travis Doom, Richard Enbody, William H. Moore, Sherry Q. Moore, Ron Sass, Charles Severance Beyond RISC — The Post-RISC Architecture (Technical Report TR96-11, Michigan State University, March 1996)