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Machine Assisted Verification

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Architecture Design and Validation Methods

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Abstract

An introduction to a number of fully mechanized methods of formal hardware verification is given. Decision-diagram based procedures for the verification of combinational circuits at the gate- and word-level are surveyed. Fixed-point calculation techniques for equivalence and property verification of sequential machines are studied. The verification of processor architectures at the instruction-set and algorithmic register-transfer level is discussed. A method of formally correct synthesis of pipelined architectures is presented.

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Authors and Affiliations

  1. Dept. of Electrical and Computer Engineering, Darmstadt University of Technology, Merckstr. 25, D-64283, Darmstadt, Germany

    Hans Eveking

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  1. Hans Eveking
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  1. Dipartimento di Informatica, Università di Pisa, Corso Italia 40, 56125, Pisa, Italy

    Egon Börger

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Eveking, H. (2000). Machine Assisted Verification. In: Börger, E. (eds) Architecture Design and Validation Methods. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-57199-2_5

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  • DOI: https://doi.org/10.1007/978-3-642-57199-2_5

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