Advertisement

Test and Testable Design

  • Hans-Joachim Wunderlich

Abstract

Defects may occur during the fabrication process and during the lifetime of integrated circuits. Integrating a faulty device into systems will result in expensive repairs or even in unsafe situations and should be avoided by testing the chips

This section explains defect mechanisms and their consequences for the product quality. Methods for test pattern generation are discussed, and it is shown how these methods can already be supported in the design phase. Modern systems-on-chip often have the capabilities of testing themselves, and recent built-in self-test techniques (BIST) are presented.

Keywords

Test Pattern Fault Coverage Linear Feedback Shift Register Fault Simulation Sequential Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Vallet, D.P., Soden, J.M.: Finding fault with deep-sub micron ICs; IEEE Spectrum, Vol. 34, No. 10 (October 1997), pp. 39–50Google Scholar
  2. 2.
    Schertz, D.R., Metze, G.: A New Representation for Faults in Combinational Digital Circuits; IEEE Transactions on Computers, Vol. 21, (August 1972), pp. 858–866Google Scholar
  3. 3.
    Maly, W., Ferguson, F.J., Shen, J.P.: Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells; Proc. ACM/IEEE International Test Conference, Philadelphia, October 1984, pp. 390–399Google Scholar
  4. 4.
    Maly, W.: Realistic Fault Modeling for VLSI Testing; Proc. 24th Design Automation Conference, Miami Beach 1987, pp. 173–180Google Scholar
  5. 5.
    Mangir, T.E.: Sources of Failures and Yield Improvement for VLSI and Restructurable Interconnects for RVLSI and WSI: Part I; Proc. IEEE, Vol. 72, No.6, (June 1984), pp. 690–708Google Scholar
  6. 7.
    Stapper, C.H.: LSI Yield Modeling and Process Monitoring; IBM Journal of Research and Development, Vol. 20, No.3, (May 1976), pp. 549–557Google Scholar
  7. 8.
    Feller, W.: An Introduction to Probability Theory and Its Applications, I; John Wiley & Sons, Third Edition, 1968Google Scholar
  8. 9.
    Nigh, P., Maly, W.: Layout-Driven Test Generation; Proc. ACM/IEEE International Conference on CAD, Santa Clara, California, 1989, pp. 154–157Google Scholar
  9. 10.
    Ferguson, F.J., Shen, J.P.: Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis; Proc. ACM/IEEE International Conference on CAD, Santa Clara, California, November 1988, pp. 475–484Google Scholar
  10. 11.
    Ferguson, F.J., Shen, J.P.: A CMOS Fault Extractor for Inductive Fault Analysis; IEEE Transactions on CAD, Vol. 7, No. 11, (November 1988), pp. 1181–1194Google Scholar
  11. 12.
    Jee, A. Ferguson, F.J.: Carafe: An Inductive Fault Analysis Tool for CMOS VLSI Circuits; Proc. IEEE Test Symposium, Atlantic City, New Jersey, April 1993, pp. 92–98Google Scholar
  12. 13.
    Corsi, F., Morandi, C.: Inductive Fault Analysis Revisited, Proc. IEEE Vol. 138, No.2, (April 1991), pp. 253–263Google Scholar
  13. 14.
    Ferris-Prabhu, A.V.: Modeling the Critical Area in Yield Forecasts; IEEE Journal on Solid-State Circuits, Vol. 20, No.4, (August 1985), pp. 874–877Google Scholar
  14. 15.
    Ferris-Prabhu, A.V.: Defect Size Variations and Their Effect on the Critical Area of VLSI Devices; IEEE Journal on Solid-State Circuits, Vol. 20, No.4, (August 1985), pp. 878–879Google Scholar
  15. 16.
    Hu, S.: Some Considerations in the Formulation of IC Yield Statistics; SolidState Electronics, Vol. 22, No.2, (February 1979), pp. 205–211Google Scholar
  16. 17.
    Stapper, C.H.: Modeling of Defects in Integrated Circuits Photolithographic Patterns; IBM Journal of Research and Development, Vo. 28, No.4, (July 1984), pp. 461–475Google Scholar
  17. 18.
    Stapper, C.H.: Modeling of Integrated Circuits Defect Sensitives; IBM Journal of Research and Development, Vol. 27, No.6, (November 1983), pp. 228–234Google Scholar
  18. 19.
    De Gyvez, J.P.: Integrated Circuit Defect-Sensitivity: Theory and Computational Models; Kluwer Academic Publishers, Boston/Dordrecht/London (1993)CrossRefGoogle Scholar
  19. 20.
    Stern, O., Wunderlich, H.-J.: Simulation Results of an Efficient Defect Analysis Procedure; Proc. ACM/IEEE International Test Conference, Washington, D.C., October 1994, pp. 729–738Google Scholar
  20. 21.
    Eldred, R.D.: Test Routines Based on Symbolic Logical Statements; Journal of the ACM, June, (1959), pp. 33–36Google Scholar
  21. 22.
    Poage, J.F.: Derivation of Optimum Tests to Detect Faults in Combinational Circuits; Proc. Symposium on Mathematical Theory of Automata; Polytechnic Press, New York, April 1963, pp. 483–528Google Scholar
  22. 23.
    Galey, J.M., Norby, R.E., Roth, J.P.: Techniques for the Diagnosis of Switching Circuit Failures; IEEE Transactions on Computers, Vol. 83, (September 1964), pp. 509–514Google Scholar
  23. 24.
    Armstrong, D.B.: On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets; IEEE Transactions on Computers, Vol. 15, (February 1966), pp. 66–73Google Scholar
  24. 25.
    Hughes, J.L.A.: Multiple Fault Detection using Single Fault Test Sets; IEEE Transactions on CAD, Vol. 7, No.1, January (1988), pp. 100–108Google Scholar
  25. 26.
    Wadsack, R.L.: Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits; Bell System Technical Journal, No.4, May (1978), pp. 1499–1474Google Scholar
  26. 27.
    Burgess, N., Damper, R.I., Totton, K.A., Shaw, D.J.: Physical Faults in MOS Circuits and Their Coverage by Different Fault Models; Proc. IEEE, Vol. 135, Pt.E, No.1 (January 1988), pp. 1–9Google Scholar
  27. 28.
    Maxwell, P.C., Aitken, R.C., Johansen, V., Chiang, I.: The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?; Proc. ACM/IEEE International Test Conference, Nashville, Tennessee, October 1991, pp. 166–177Google Scholar
  28. 29.
    Hsieh, E.P. et al.: Delay Test Generation, Proc. 14th ACM/IEEE Design Automation Conference, June 1977, pp. 486–491Google Scholar
  29. 30.
    Smith, G.L.: Model for Delay Faults Based On Paths, Proc. International Test Conference, 1985, pp. 342–349Google Scholar
  30. 31.
    Abraham, J.A., Fuchs, W.K: Fault and Error Models for VLSI; Proc. IEEE, Vol. 74, No.5, (May 1986), pp. 639–654Google Scholar
  31. 32.
    Al-Arian, S.A., Agrawal, D.P.: Physical Failures and Fault Models of CMOS Circuits; IEEE Transactions on Circuits and Systems, Vol. 34, No.3 (1987), pp.269–279Google Scholar
  32. 33.
    Champac, V.H., Rodrigues-Montanes, R., Segura, J.A., Figueras, J., Rubio, J.A.: Fault Modeling of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS Circuits; Proc. European Test Conference, Munich, April 1991, pp. 143–148Google Scholar
  33. 34.
    Hawkins, C.F., Soden, J.M., Righter, A.W., Ferguson, F.J.: Defect Classes-An Overdue Paradigm for CMOS IC Testing; Proc. ACM/IEEE International Test Conference, Washington, D.C., October 1994, pp. 413–425Google Scholar
  34. 35.
    Johnson, S.: Residual Charge on the Faulty Floating Gate MOS Transistor, Proc. IEEE International Test Conference, Washington, D.C., October 1994, pp. 555–571Google Scholar
  35. 36.
    Su, S.Y.H., Koren, I., Malaiya, Y.K.: Diagnosis of intermittent faults in combinational networks; IEEE Transactions on Computers, Vol. 37, No. 10, October 1988, pp. 1309–1314Google Scholar
  36. 37.
    Malaiya, Y.K, Su, S.Y.H.: A new fault model and testing technique for CMOS devices; Proc. International Test Conference, 1982, pp. 25–34Google Scholar
  37. 38.
    Soden, J.M., Hawkins, C.F.: Test consideration for gate oxide shorts in CMOS ICs; IEEE Design and Test, August 1986, pp. 56–64Google Scholar
  38. 39.
    Isern, E., Figueras, J.: Test generation with high coverages for quiescent current test of bridging fault in combinational circuits; Proc. IEEE International Test Conference, Washington, D.C., 1993, pp. 73–82Google Scholar
  39. 40.
    Maly, W., Nigh, P.: Built-In Current Testing-A Feasibility Study; Proc. IEEE International Conference on CAD, Santa Clara 1988, pp. 340–343Google Scholar
  40. 41.
    Rubio, A., Figueras, J., Segura, J.: Quiescent current sensor circuits in digital VLSI CMOS testing; Electronics Letters, Vol. 26, No. 15, (1990), pp. 1204–1206Google Scholar
  41. 42.
    Rius, R., Figueras, J.: Proportional BIC Sensor for Curent Testing; Journal of Electronic Testing: Theory and Applications, JETTA, Vol. 3, No.4, (December 1992), pp. 387–396Google Scholar
  42. 43.
    Keating, M., Meyer, D.: A new approach to dynamic IDD testing, Proc. International Test Conference, 1987, pp. 316–321Google Scholar
  43. 44.
    Maly, W., Patyra, M.: Design of ICs Applying Built-In Current Testing; Journal o. Electronic Testing: Theory a. Applications, JETTA, Vol. 3, No.4, (December 1992) pp. 397–406Google Scholar
  44. 45.
    Wunderlich, H.-J., Herzog, M., Figueras, J., Carrasco, J.A., Calderon, A.: Synthesis of IDDQ-Testable Circuits: Integrating Built-In Current Sensors; Proc. European Design & Test Conference, Paris, March 1995, pp. 573–580Google Scholar
  45. 46.
    Williams, T.W., et. al.: IDDQ Test: Sensitivity Analysis of Scaling; Proc. IEEE International Test Conference, Washington, D.C., 1996, pp. 786–792Google Scholar
  46. 47.
    Sachdev, M.: Deep Sub-micron Testing: Issues and Solutions; Proc. European Design & Test Conference (1997), pp. 271–278Google Scholar
  47. 48.
    Williams, T.W., Brown, N.C.: Defect Level as a Function of Fault Coverage; IEEE Transactions on Computers, Vol. 30, No. 12, (December 1981)Google Scholar
  48. 49.
    Roth, J.P.: Diagnosis of Automata Failures. A Calculus and a Method; IBM Journal of Research and Development, Vol. 9, No.2 (1966)Google Scholar
  49. 50.
    Fujiwara, H., Shimono, T.: On the Acceleration of Test Generation; IEEE Transactions on Computers, Vol. 32 (1983), pp. 1137–1144Google Scholar
  50. 51.
    Schulz, M., et. al.: SOCRATES: A Highly Efficient Automatic Test Pattern Generation System; IEEE Transactions on CAD, Vol. 7 (1988), pp. 30–35Google Scholar
  51. 52.
    Kunz, W., Pradhan, D.K.: Recursive Learning: An Attractive Alternative to the Decision Tree for Test Generation in Digital Circuits; Proc. International Test Conference, 1992, pp. 816–825Google Scholar
  52. 53.
    Niermann, T.M, Patel, J.H.: HITEC: A test generation package for sequential circuits; Proc. European Conference on Design Automation, February 1991Google Scholar
  53. 54.
    Waicukauski et. al.: ATPG for Ultra-Large Structured Designs; Proc. International Test Conference, Washington, D.C., 1990, pp. 44–51Google Scholar
  54. 55.
    Bershteyn, M.: Calculation of Multiple Sets of Weights for Weighted Random Testing; Proc. IEEE International Test Conference, Washington, D.C., 1993, pp. 1031–1040Google Scholar
  55. 56.
    Krieger, R., Becker, B., Sinkovic, R.: A BDD-based Algorithm for Computation of Exact Fault Detection Probabilities; Proc. 23rd International Symposium on Fault-Tolerant Computing (1993), pp. 186–195Google Scholar
  56. 57.
    Lisanke, R., Brglez, F., Degeus, A.J., Gregory, D.: Testability Driven Random Test-Pattern Generation; IEEE Transactions on CAD, Vol. 6, No.6, (November 1987), pp. 660–669Google Scholar
  57. 58.
    Waicukauski, J.A., Lindbloom, E., Eichelberger, E.B., Forlenza, O.P.: A Method for Generating Weighted Random Test Patterns; IBM Journal of Research and Development, Vol. 33, No.2, (March 1989), pp. 149–161Google Scholar
  58. 59.
    Wunderlich, H.-J.: PROTEST: A Tool for Probabilistic Testability Analysis; Proc. 22nd ACM/IEEE Design Automation Conference, Las Vegas, 1985, pp. 204–211Google Scholar
  59. 60.
    Kapur, R., Patil, S., Snethen, T.J., Williams, T.W.: Design of an Efficient Weighted Radnom Pattern Generation System; Proc. IEEE International Test Conference, 1994, pp. 491–500Google Scholar
  60. 61.
    Muradali, F., Agarwal, V.K., Nadeau-Dostie, B.: A New Procedure for Weighted Random Built-In Self-Test; Proc. IEEE International Test Conference, 1990, pp. 660–669Google Scholar
  61. 62.
    Patera, S., Rajski, J.: Cube-Contained Random Patterns and their Application to the Complete Testing of Synthesized Multi-level Circuits; Proc. IEEE International Test Conference, 1991, pp. 473–482Google Scholar
  62. 63.
    Pomeranz, I., Reddy, S.M.: 3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set for Combinational and Sequential Circuits; IEEE Transactions on CAD, Vol. 12, No.7 (1993) pp. 1050–1058Google Scholar
  63. 64.
    Reeb, B., Wunderlich, H.-J.: Deterministic Pattern Generation for Weighted Random Pattern Testing; Proc. European Design & Test Conference, Paris, March 1996, pp. 30–36Google Scholar
  64. 65.
    Waicukauski, J., Lindbloom, E.: Fault Detection Effectiveness of Weighted Random Patterns; Proc. International Test Conference, Washington, D.C., 1988, pp. 245–256Google Scholar
  65. 66.
    Waicukauski, J.A., et. al.: Fault Simulation for Structured VLSI; VLSI Systems Design, December 1985, pp. 20–32Google Scholar
  66. 67.
    Antreich, K.J., Schulz, M.H.: Accelerated Fault Simulation and Fault Grading in Combinational Circuits; IEEE Transactions on CAD, Vol. 6 (1987), pp. 704–712.Google Scholar
  67. 68.
    Williams, M.J.Y., Angell, J.B.: Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic; IEEE Transactions on Computers, Vol. 22, No.1 (1973)Google Scholar
  68. 69.
    Eichelberger, E.B., Williams, T.W.: A logic design structure for LSI testability; Proc. 14th Design Automation Conference, June 1977, pp. 462–468Google Scholar
  69. 70.
    Cheng, K.-T., Agrawal, V.D.: A Partial Scan Method for Sequential Circuits with Feedback; IEEE Transactions on Computers, Vol. 39, No.4, (April 1990), pp. 544–547Google Scholar
  70. 71.
    Chakradhar, S.T., Balakrishnan, A., Agrawal, V.D.: An Exact Algorithm for Determining Partial Scan Flip-Flops; Proc. Design Automation Conference, San Diego, 1994Google Scholar
  71. 72.
    Gupta, R., Gupta, R., Breuer, M.A.: The BALLAST Methodology for Structured Partial Scan Design; IEEE Transactions on Computers, April (1990), pp. 538–544Google Scholar
  72. 73.
    Kunzmann, A., Wunderlich, H.-J.: An analytical approach to the partial scan problem; Journal of Electronic Testing: Theory and Applications (1990), pp. 163–174Google Scholar
  73. 74.
    Hayes, J.P., Friedmann, A.D.: Test Point Placement to Simplify Fault Detection; IEEE Transactions on Computers, Vol. 33, (July 1974), pp. 727–735Google Scholar
  74. 75.
    Seiss, B.H., Troubourst, P.M., Schulz, M.H.: Test Point Insertion for Scan Based BIST; Proc. European Test Conference, 1991, pp. 253–262Google Scholar
  75. 76.
    Wunderlich, H.-J., Hellebrand, S.: The Pseudo-Exhaustive Test of Sequential Circuits; IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 11, No.1 (January 1992), pp. 26–33Google Scholar
  76. 77.
    Eichelberger, E.B., Lindbloom, E.: Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test; IBM Journal of Research and Development, Vol. 27, No.3, (May 1983)Google Scholar
  77. 78.
    Bardell, P.H.; McAnney, W.H.: Self-testing of multichip logic modules; Proc. IEEE International Test Conference, 1982, pp. 200–204Google Scholar
  78. 79.
    Koenemann, B., et. al.: Built-In Logic Block Observation Techniques; Proc. Test Conference, Cherry Hill, New Jersey, 1979Google Scholar
  79. 80.
    Craig, G.L., Kime, C.R, Saluja, K.K.: Test Scheduling and Control for VLSI Built-In Self-Test; IEEE Transactions on Computers, September (1988), pp. 1099–1109Google Scholar
  80. 81.
    Stroele, A.P., Wunderlich, H.-J.: Signature Analysis and Test Scheduling for Self-Testable Circuits; Proc. International Symposium on Fault-Tolerant Computing, Montreal, 1991, pp. 96–103Google Scholar
  81. 82.
    Girard, P., Landrault, C., Moréda, V., Pravossoudovitch, S.: An Optimized BIST Test Pattern Generator for Delay Testing; Proc. of 15th VLSI Test Symposium, April 1997, pp. 94–99Google Scholar
  82. 83.
    Peterson, W.W., Weldon, E.J., Jr.: Error-Correcting Codes; MIT-Press, Cambridge, Massachusetts, London, 1972MATHGoogle Scholar
  83. 84.
    Lidl, R., Niederreiter, H.: Introduction to finite fields and their applications; Cambridge: Cambridge University Press (1986)MATHGoogle Scholar
  84. 85.
    Golomb, S.W.: Shift Register Sequences; Aegan Park Press, Laguna Hills, 1982Google Scholar
  85. 86.
    Chen, C.L.: Linear Dependencies in Linear Feedback Shift Registers; IEEE Transactions on Computers, Vol. 35, No. 12 (1986), pp. 1086–1088Google Scholar
  86. 87.
    Serra, M., Slater, T., Muzio, J.C., Miller, D.M.: The Analysis of One Dimensional Linear Cellular Automata and Their Aliasing Properties; IEEE Transactions on CAD, Vol. 9, No.7, (July 1990), pp. 767–778Google Scholar
  87. 88.
    Williams, T.W., Daehn, W., Gruetzner, W., Starke, C.W.: Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials; Proc. IEEE International Test Conference, Philadelphia, September (1986), pp. 282–288Google Scholar
  88. 89.
    Damiani, et. al.: Aliasing in Signature Analysis Testing with Multiple-Input Shift-Registers; Proc. 1st European Test Conference, Paris, 1989, pp. 346–353Google Scholar
  89. 90.
    Savir, J.: Syndrome-Testable Design of Combinational Circuits; IEEE Transactions on Computers, Vol. 26, No.6 (1980)Google Scholar
  90. 91.
    Krasniewski, A., Pilarski, S.: Circular Self-Test Path: A Low-Cost BIST Technique for LVSI Circuits; IEEE Transactions on CAD, Vol. 8, No.1, (January 1989), pp. 46–55Google Scholar
  91. 92.
    Wang, L.T., McCluskey, E.J.: Concurrent Built-in Logic Block Observer (CBILBO); Proc. International Symposium on Circuits and Systems, 1986, pp. 1054–1057Google Scholar
  92. 93.
    Stroele, A., Wunderlich, H.-J.: Configuring Flip-Flops to BIST registers; Proc. IEEE International Test Conference, Washington, D.C., 1994, pp. 939–948Google Scholar
  93. 94.
    Savir, J., McAnney, W.H.: A Multiple Seed Linear Feedback Shift Register; IEEE Transactions on Computer, February (1992), pp. 250–252Google Scholar
  94. 95.
    Lempel, M., Gupta, S.K, Breuer, M.A.: Test Embedding with Discrete Logarithms; IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 14, No.5, (May 1995), pp. 554–566Google Scholar
  95. 96.
    Mukund, S.K., McCluskey, E.J., Roo, T.R.N.: An Apparatus for Pseudo-Deterministic Testing; Proc. 13th VLSI Test Symposium, Princeton, NJ, 1995, pp. 125–131Google Scholar
  96. 97.
    Hellebrand, S., Wunderlich H.-J., Hertwig, A.: Mixed-Mode BIST Using Embedded Processors; Proc. IEEE International Test Conference, Washington, D.C., 1996, pp. 195–204Google Scholar
  97. 98.
    Akers, S.B., Jansz, W.: Test Set Embedding in Built-in Self-Test Environment; Proc. IEEE International Test Conference, Washington, D.C., 1989, pp. 257–263Google Scholar
  98. 99.
    Chatterjee, M., Pradhan, D.K.: A Novel Pattern Generator for Near-Perfect Fault-Coverage; Proc. 13th VLSI Test Symposium, Princeton, NJ, 1995, pp. 417–425Google Scholar
  99. 100.
    Touba, N.A., McCluskey, E.J.: Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST; Proc. IEEE International Test Conference, Washington, D.C., 1995, pp. 674–682Google Scholar
  100. 101.
    Koenemann, B.: LFSR-Coded Test Patterns for Scan Designs; Proc. European Test Conference, Munich, 1991, pp. 237–242Google Scholar
  101. 102.
    Wunderlich, H.-J., Kiefer, G.: Bit-Flipping BIST; Proc. IEEE/ACM International Conference on CAD, San Jose, CA, November 1996, pp. 337–343Google Scholar
  102. 103.
    Hellebrand, S., Tarnick, S., Rajski, J., Courtois, B.: Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers; Proc. IEEE International Test Conference, Baltimore, MD, September 1992, pp. 120–129Google Scholar
  103. 104.
    Hellebrand, S., Rajski, J., Tarnick, S., Venkataraman, S., Courtois, B.: Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers; IEEE Transactions on Computers, Vol. 44, No.2, (February 1995), pp. 223–233Google Scholar
  104. 105.
    Hellebrand, S., Reeb, B., Tarnick, S., Wunderlich, H.-J.; Pattern Generation for a Deterministic BIST Scheme: Proc. IEEE/ACM International Conference on CAD, San Jose, CA, November 1995, pp. 88–94Google Scholar
  105. 106.
    Rajski, J., Tyszer, J.: Test Responses Compaction in Accumulators with Rotate Carry Adders; IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 12, No.4, (April 1993), pp. 531–539Google Scholar
  106. 107.
    Gupta, S., Rajski, J., Tyszer, J.: Arithmetic Adaptive Generators of PseudoExhaustive Test Patterns; IEEE Transactions on Computers, Vol. 8, No. 45, (August 1996), pp. 939–949Google Scholar
  107. 108.
    Stroele, A.P.: Arithmetic Pattern Generators for Built-In Self-Test; Proc. International Conference on Computer-Aided Design, 1996, pp. 131–134Google Scholar
  108. 109.
    Stroele, A.P.: BIST Pattern Generators using Addition and Subtraction Operations; Journal of Electronic Testing: Theory and Applications, JETTA, Vol. 11, No.1. (August 1997), pp. 68–80Google Scholar
  109. 110.
    Rajski, J., Tyszer, J.: Multiplicative Window Generators of Pseudo-Random Test Vectors; Proc. European Design and Test Conference, 1996, pp. 186–194Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Hans-Joachim Wunderlich
    • 1
  1. 1.Institute of Computer ScienceUniversity of StuttgartStuttgartGermany

Personalised recommendations