Abstract
The narrowest feature on an integrated circuit is currently the gate oxide. At the end of the last century, gate oxides less than 20 Å were used in some commercial integrated circuits. Between 2004 and 2008, if silicon dioxide is still to be used, then the projected gate-oxide thickness will be less than 1 nm, or 5 silicon atoms across. At least two of those five atoms will be at silicon/oxide interfaces. The interfacial atoms have very different electrical and optical properties from the desired bulk silicon dioxide yet comprise a significant fraction of the dielectric layer. This fundamental problem has also become a very practical one. It is now technologically possible to produce metal oxide semiconductor field effect transistors (MOSFETs) with gates shorter than 50nm and SiO2 gate oxides less than 1.3nm thick [1]. Such a thin gate oxide is required to improve the drain-current response of the transistor to the applied gate voltage (allowing lower voltages to be used). Since power dissipation currently limits the scale of integration, lowering the power supply voltage becomes the key to increasing integration and improving IC performance. Therefore, the performance of the gate oxides is central to the improvement of very large-scale integrated circuits. Since a practical alternative to SiO2 (or its nitrogenated derivatives), providing a higher dielectric constant or a reduced leakage current, has not been identified yet [2], it is crucial to the future of large-scale integration to discover the practical limits on the thickness of the SiO2 gate oxide.
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Keywords
- Scanning Transmission Electron Microscope
- Electron Energy Loss Spectroscopy
- Gate Oxide
- Interface Roughness
- Core Hole
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Muller, D.A., Neaton, J.B. (2001). Evolution of the Interfacial Electronic Structure During Thermal Oxidation. In: Chabal, Y.J. (eds) Fundamental Aspects of Silicon Oxidation. Springer Series in Materials Science, vol 46. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-56711-7_11
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