Reduced Order Modelling of RLC-networks Using an SVD-Laguerre Based Method
With interconnect increasingly contributing to the electrical behaviour of integrated circuits, both by higher frequencies and smaller dimensions, it becomes increasingly important to incorporate its behaviour into simulations of ICs. This can be done rather elegantly by summarizing interconnect behaviour into a compact or reduced order model which is then co-simulated with the circuit. A similar approach can be used in the case of more conventional printed circuit boards. The SVD-Laguerre algorithm proposed by Knockaert and De Zutter  can be used for this purpose. In this paper, we describe an efficient implementation of the algorithm for multiple inputs, and show how the mathematical reduced order models can be translated into realizable circuit elements.
KeywordsSingular Value Decomposition Boundary Element Method Reduce Order Modelling Krylov Subspace Krylov Subspace Method
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