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Reduced Order Modelling of RLC-networks Using an SVD-Laguerre Based Method

  • Pieter Heres
  • Wil Schilders
Part of the Mathematics in Industry book series (MATHINDUSTRY, volume 4)

Abstract

With interconnect increasingly contributing to the electrical behaviour of integrated circuits, both by higher frequencies and smaller dimensions, it becomes increasingly important to incorporate its behaviour into simulations of ICs. This can be done rather elegantly by summarizing interconnect behaviour into a compact or reduced order model which is then co-simulated with the circuit. A similar approach can be used in the case of more conventional printed circuit boards. The SVD-Laguerre algorithm proposed by Knockaert and De Zutter [4] can be used for this purpose. In this paper, we describe an efficient implementation of the algorithm for multiple inputs, and show how the mathematical reduced order models can be translated into realizable circuit elements.

Keywords

Singular Value Decomposition Boundary Element Method Reduce Order Modelling Krylov Subspace Krylov Subspace Method 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Pieter Heres
    • 1
  • Wil Schilders
    • 1
    • 2
  1. 1.Department of Mathematics and Computing Science, Scientific Computing GroupEindhoven University of TechnologyEindhovenThe Netherlands
  2. 2.Philips Research LaboratoryEindhovenThe Netherlands

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