Abstract
This paper describes three hierarchical organizations of small processors for bottom-up image analysis: pyramids, interleaved pyramids, and pyramid trees. Progressively lower levels in the hierarchies process image windows of decreasing size. Bottom-up analysis is made feasible by transmitting up the levels quadrant borders and border-related information that captures quadrant interaction of interest for a given computation. The operation of the pyramid is illustrated by examples of standard algorithms for interior-based computations (e.g., area) and border-based computations of local properties (e.g., perimeter). A connected component-counting algorithm is described that illustrates the role of border-related information in representing quadrant interaction. Interleaved pyramids are obtained by sharing processors among several pyramids. They increase processor utilization and throughput rate at the cost of increased hardware. Trees of shallow interleaved pyramids, called pyramid trees, are introduced to reduce the hardware requirements of large interleaved pyramids at the expense of increased processing time, without sacrificing processor utilization. The three organizations are compared with respect to several performance measures.
This research was supported by the Joint Services Electronics Program (U.S. Army, Navy and Air Force) under Contract N00014-79-C-0424.
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Ahuja, N., Swamy, S. (1984). Multiprocessor Pyramid Architectures for Bottom-Up Image Analysis. In: Rosenfeld, A. (eds) Multiresolution Image Processing and Analysis. Springer Series in Information Sciences, vol 12. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-51590-3_3
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DOI: https://doi.org/10.1007/978-3-642-51590-3_3
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