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Towards a VLIW Architecture for the 32-Bit Digital Signal Processor Core

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Part of the Lecture Notes in Electrical Engineering book series (LNEE,volume 279)

Abstract

Digital Signal Processors have been developed for ages due to the great effectiveness in digital signal processing algorithms such as digital filtering and Fourier analysis which cannot be achieved in general-purpose processors. This work is to propose a VLIW architecture for Digital Signal Processor core including the top-level design of the data path. RTL implementation of the proposed architecture will be carried out in the future to verify the micro-architecture as well as instruction set of the DSP core.

Keywords

  • Digital Signal Processor
  • VLIW Architecture

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Correspondence to Khoi-Nguyen Le-Huu .

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Le-Huu, KN., Vu, T.T., Ho, D.N., Dinh-Duc, AV. (2014). Towards a VLIW Architecture for the 32-Bit Digital Signal Processor Core. In: Jeong, H., S. Obaidat, M., Yen, N., Park, J. (eds) Advances in Computer Science and its Applications. Lecture Notes in Electrical Engineering, vol 279. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41674-3_109

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  • DOI: https://doi.org/10.1007/978-3-642-41674-3_109

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-41673-6

  • Online ISBN: 978-3-642-41674-3

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