Behavioural Verification in Embedded Software, from Model to Source Code

  • Anthony Fernandes Pires
  • Thomas Polacsek
  • Virginie Wiels
  • Stéphane Duprat
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8107)


To reduce the verification costs and to be more confident on software, static program analysis offers ways to prove properties on source code. Unfortunately, these techniques are difficult to apprehend and to use for non-specialists. Modelling allows users to specify some aspects of software in an easy way. More precisely, in embedded software, state machine models are frequently used for behavioural design. The aim of this paper is to bridge the gap between model and code by offering automatic generation of annotations from model to source code. These annotations are then verified by static analysis in order to ensure that the code behaviour conforms to the model-based design. The models we consider are UML state machines with a formal non-ambiguous semantics, the annotation generation and verification is implemented in a tool and applied to a case study.


Verification UML Formal Methods Model Driven Engineering 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Anthony Fernandes Pires
    • 1
    • 2
  • Thomas Polacsek
    • 1
  • Virginie Wiels
    • 1
  • Stéphane Duprat
    • 2
  1. 1.ONERAToulouseFrance
  2. 2.Atos Intégration SASToulouse cedex 03France

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