Speed and Size-Optimized Implementations of the PRESENT Cipher for Tiny AVR Devices

Conference paper

DOI: 10.1007/978-3-642-41332-2_11

Part of the Lecture Notes in Computer Science book series (LNCS, volume 8262)
Cite this paper as:
Papagiannopoulos K., Verstegen A. (2013) Speed and Size-Optimized Implementations of the PRESENT Cipher for Tiny AVR Devices. In: Hutter M., Schmidt JM. (eds) Radio Frequency Identification. RFIDSec 2013. Lecture Notes in Computer Science, vol 8262. Springer, Berlin, Heidelberg

Abstract

This paper presents high-speed and low-size assembly implementations of the 80-bit version of the PRESENT cipher for the (Tiny)AVR family of microcontrollers. We report new speed and size records for our implementations, with the speed-optimized version achieving a full encryption in 8721 clock cycles and the size-optimized version compressing the cipher down to 272 bytes; the previous state of the art for (Tiny)AVR achieved 10723 clock cycles for encryption with a size of 936 bytes. Along with the two implementation extrema (speed and size optimized versions), we offer insight into techniques and representations that show the speed/area tradeoffs and provide intermediate solutions for various configurations.

Keywords

PRESENT AVR ATtiny Assembly software implementation 

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Radboud Universiteit NijmegenNijmegenThe Netherlands

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