Multicast Algorithm for 2D de Bruijn NoCs

  • Reza Sabbaghi-Nadooshan
  • Abolfazl Malekmohammadi
  • Mohammad Ayoub Khan
Part of the Studies in Computational Intelligence book series (SCI, volume 520)


The performance of the network is measured in terms of throughput. The throughput and efficiency of interconnect depends on network parameters of the topology. Therefore, topology of any communication networks has an important role to play for efficient design of network. The De Bruijn topology has the potential to be an interesting option for future generations of System-on-Chip (SoC). Two-dimensional (2-D) de Bruijn is proposed for Networks-on-Chips (NoCs) applications. We can improve performance in the two dimensional Bruijn NoCs by improvement of routing algorithm. In this chapter, we have proposed a multicast routing algorithm for 2-D de Bruijn NoCs. The proposed routing algorithm is compared with unicast routing using Xmulator under various traffics conditions. Based on comparison results, the proposed routing has significantly improved the performance and power consumption of the NoC in comparison with unicast routing under light and moderate traffic loads in hot spot and uniform traffics with various message lengths.


  1. 1.
    A. Jantsch, H. Tenhunen, Network on Chip (Kluwer Academic Publishers, Dordrecht, 2003)Google Scholar
  2. 2.
    W.J. Dally, H. Aoki, Deadlock-free adaptive routing in multicomputer networks using virtual channels. IEEE Trans. Parallel Distrib. Syst. 4, 466–475 (1993)CrossRefGoogle Scholar
  3. 3.
    P.P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh, Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput. 54, 1025–1040 (2005)Google Scholar
  4. 4.
    E. Salminen, A. Kulmala, T.D. Hamalainen, Survey of network-on-chip proposals. OCP-IP white paper (2008)Google Scholar
  5. 5.
    A. Flores, J.L. Aragon, M.E. Acacio, An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. J. Supercomputing 45, 341–364 (2008)CrossRefGoogle Scholar
  6. 6.
    U.Y. Ogras, R. Marculescu, Application-specific network-on-chip architecture customization via long-range link insertion. IEEE/ACM International Conference on Computer Aided Design (2005)Google Scholar
  7. 7.
    M. Chatti, S. Yehia, C. Timsit, S. Zertal, A hypercube-based NoC routing algorithm for efficient all-to-all communications in embedded image and signal processing applications. HPCS 623–630 (2010)Google Scholar
  8. 8.
    H. Matsutani, M. Koibuchi, Y. Yamada, H. Amano, Fat H-tree: a cost-effective tree-based on-chip-networks. IEEE Trans. Parallel Distrib. Syst. 20, 1126–1141 (2009)CrossRefGoogle Scholar
  9. 9.
    N.G. de Bruijn, A combinatorial Problem. Koninklijke Nederlands Akad. van Wetenschappen Proc. 49, 758–764 (1946)Google Scholar
  10. 10.
    M.R. Samanathan, D.K. Pradhan, The de Bruijn multiprocessor network: a versatile parallel processing and sorting network for VLSI. IEEE Trans. Comp. 38, 567–581 (1989)CrossRefGoogle Scholar
  11. 11.
    E. Ganesan, D.K. Pradhan, Wormhole routing in de Bruijn networks and Hyper-de Bruijn Networks, in IEEE International Symposium on Circuits and Systems (ISCAS) (2003), pp. 870–873Google Scholar
  12. 12.
    H. Park, D.P. Agrawal, A novel deadlock-free routing technique for a class of de Bruijn based networks, in 7th IEEE Symposium on Parallel and Distributed Processing (1995), pp. 92–97Google Scholar
  13. 13.
    M. Hosseinabady, J. Mathew, D.K. Pradhan, Application of de Bruijn graphs to NoC. DATE (2007), pp. 111–116Google Scholar
  14. 14.
    R. Sabbaghi-Nadooshan, M. Modarressi, H. Sarbazi-Azad, The 2d DBM: an attractive alternative to the mesh topology for network-on-chip, in IEEE International Conference on Computer Design (2008), pp. 486–490Google Scholar
  15. 15.
    R. Sabbaghi-Nadooshan, M. Modarressi, H. Sarbazi-Azad, The 2D digraph-based NoCs: attractive alternatives to the 2D mesh NoCs. J. Supercomputing 49, 1–21 (2012)CrossRefGoogle Scholar
  16. 16.
    R. Sabbaghi-Nadooshan, H. Sarbazi-Azad, The kautz mesh: a new topology for SoCs, in International Conference on SoC Design (2008), pp. 300–303Google Scholar
  17. 17.
    G.P. Liu, K.Y. Lee, Optimal routing algorithms for generalized de Bruijn digraph, inInternational Conference on Parallel Processing (1993), pp. 167–174Google Scholar
  18. 18.
    J. Mao, C. Yang, Shortest path routing and fault-tolerant routing on de Bruijn networks. Networks 35, 207–215 (2000)MathSciNetCrossRefMATHGoogle Scholar
  19. 19.
    A. Nayebi, S. Meraji, A. Shamaei, H. Sarbazi-Azad, Xmulator: a listener-based integrated simulation platform for interconnection networks, in Proceedings of Asian International Coneference on Modelling and Simulation (2007), pp. 128–132Google Scholar
  20. 20.
    J. Duato, S. Yalamanchili, L.M. Ni, Interconnection Networks. Morgan Kaufman (2003)Google Scholar
  21. 21.
    R. Sabbaghi-Nadooshan, M. Modarressi, H. Sarbazi-Azad, 2D SEM: a novel high-performance and low-power mesh-bases topology for networks-on-chip. Int. J. Parallel Emergent Distrib. Syst. 25, 331–344 (2010)MathSciNetCrossRefMATHGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2014

Authors and Affiliations

  • Reza Sabbaghi-Nadooshan
    • 1
  • Abolfazl Malekmohammadi
    • 1
  • Mohammad Ayoub Khan
    • 2
  1. 1.Electrical Engineering DepartmentIslamic Azad University Central Tehran BranchTehranIran
  2. 2.Department of Computer Science and EngineeringSharda University, GreaterNoidaIndia

Personalised recommendations