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Microscopic Bit-Level Wear-Leveling for NAND Flash Memory

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Part of the Lecture Notes in Electrical Engineering book series (LNEE,volume 274)


By microscopically observing widely used data files, we identified the considerable room for life time improvement in NAND flash memory, which is due to the discovery of a non-uniformity in bit-level data patterns. In an attempt to exploit the discovery, we propose a novel bit-level wear-leveling scheme. Instead of considering only the view of page-level or block-level, we incorporate the non-uniformity in data encoding patterns into wear-leveling scheme. Because of its orthogonality to the existing block-level wear-leveling approaches, our solution can be adopted over the existing solutions without considerable overhead and extend NAND flash’s life span up to 36% in case of SLC.


  • Data Pattern
  • Page Size
  • NAND Flash
  • Tunnel Oxide
  • Error Correction Algorithm

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  • DOI: 10.1007/978-3-642-40675-1_48
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  1. DBT2 benchmark,

  2. Bin, Z.W., Ming, X., Zheng, X., Kang, Z.A.: Charge-to-breakdown (Q BD ): a method to monitor the ultrathin tunnel oxide in E2PROM. In: Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology, pp. 287–290 (1998)

    Google Scholar 

  3. Chang, L.-P., Huang, L.-C.: A low-cost wear-leveling algorithm for block-mapping solid-state disks. SIGPLAN Not. 46(5), 31–40 (2011)

    MathSciNet  CrossRef  Google Scholar 

  4. Chang, L.-P., Kuo, T.-W.: Efficient management for large-scale flash-memory storage systems with resource conservation. TOS 1(4), 381–418 (2005)

    CrossRef  Google Scholar 

  5. Chang, Y.-H., Hsieh, J.-W., Kuo, T.-W.: Improving flash wear-leveling by proactively moving static data. IEEE Trans. Computers 59(1), 53–65 (2010)

    MathSciNet  CrossRef  Google Scholar 

  6. Hussain, S.A., Mansoor, A.: Flash modelling for wearleveling algorithms. In: High Capacity Optical Networks and Enabling Technologies (HONET), pp. 267–272 (December 2011)

    Google Scholar 

  7. Murugan, M., Du, D.H.-C.: Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead. In: Brinkmann, A., Pease, D. (eds.) MSST, pp. 1–12. IEEE Computer Society (2011)

    Google Scholar 

  8. SQLite. Sqlite official home page,

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Correspondence to Yong Song .

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Song, Y., Hwang, W., Park, KW., Park, K.H. (2014). Microscopic Bit-Level Wear-Leveling for NAND Flash Memory. In: Park, J., Adeli, H., Park, N., Woungang, I. (eds) Mobile, Ubiquitous, and Intelligent Computing. Lecture Notes in Electrical Engineering, vol 274. Springer, Berlin, Heidelberg.

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  • Print ISBN: 978-3-642-40674-4

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