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Microscopic Bit-Level Wear-Leveling for NAND Flash Memory

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Part of the Lecture Notes in Electrical Engineering book series (LNEE,volume 274)

Abstract

By microscopically observing widely used data files, we identified the considerable room for life time improvement in NAND flash memory, which is due to the discovery of a non-uniformity in bit-level data patterns. In an attempt to exploit the discovery, we propose a novel bit-level wear-leveling scheme. Instead of considering only the view of page-level or block-level, we incorporate the non-uniformity in data encoding patterns into wear-leveling scheme. Because of its orthogonality to the existing block-level wear-leveling approaches, our solution can be adopted over the existing solutions without considerable overhead and extend NAND flash’s life span up to 36% in case of SLC.

Keywords

  • Data Pattern
  • Page Size
  • NAND Flash
  • Tunnel Oxide
  • Error Correction Algorithm

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Correspondence to Yong Song .

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© 2014 Springer-Verlag Berlin Heidelberg

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Song, Y., Hwang, W., Park, KW., Park, K.H. (2014). Microscopic Bit-Level Wear-Leveling for NAND Flash Memory. In: Park, J., Adeli, H., Park, N., Woungang, I. (eds) Mobile, Ubiquitous, and Intelligent Computing. Lecture Notes in Electrical Engineering, vol 274. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-40675-1_48

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  • DOI: https://doi.org/10.1007/978-3-642-40675-1_48

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-40674-4

  • Online ISBN: 978-3-642-40675-1

  • eBook Packages: EngineeringEngineering (R0)