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Microscopic Bit-Level Wear-Leveling for NAND Flash Memory

  • Yong SongEmail author
  • Woomin Hwang
  • Ki-Woong Park
  • Kyu Ho Park
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 274)

Abstract

By microscopically observing widely used data files, we identified the considerable room for life time improvement in NAND flash memory, which is due to the discovery of a non-uniformity in bit-level data patterns. In an attempt to exploit the discovery, we propose a novel bit-level wear-leveling scheme. Instead of considering only the view of page-level or block-level, we incorporate the non-uniformity in data encoding patterns into wear-leveling scheme. Because of its orthogonality to the existing block-level wear-leveling approaches, our solution can be adopted over the existing solutions without considerable overhead and extend NAND flash’s life span up to 36% in case of SLC.

Keywords

Data Pattern Page Size NAND Flash Tunnel Oxide Error Correction Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2014

Authors and Affiliations

  • Yong Song
    • 1
    Email author
  • Woomin Hwang
    • 1
  • Ki-Woong Park
    • 2
  • Kyu Ho Park
    • 1
  1. 1.CORE Lab., Dept. of Electrical EngineeringKAISTDaejeonKorea
  2. 2.Dept. of Computer Hacking and Information SecurityDaejeon UniversityDaejeonKorea

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