Abstract
The Network-on-Chip (NoC) paradigm plays an essential role in designing emerging multicore processors. Three Dimensional (3D) NoC design expands the on-chip network vertically. To achieve high performance in a 3D NoC, it is crucial to reduce the access latency of caches and memories. In this paper, we propose an optimized design that provides high performance, low power consumption and manufacturing cost. The proposed scheme shifts the fully connected mesh network to a partially connected network, with the optimization of heterogeneous routers and links. Full system evaluation shows that, compared to a previous optimized heterogeneous design, OPTNOC can further reduce the execution time by 12.1% and energy delay product by 23.5%.
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References
Dally, W.J., et al.: Route packets, not wires: on-chip inteconnection networks. In: Proceedings of the 38th DAC, pp. 684–689 (June 2001)
Velenis, D., et al.: Impact of 3d design choices on manufacturing cost. In: IEEE 3DIC 2009, pp. 1–5 (September 2009)
Xu, T., et al.: Optimal number and placement of through silicon vias in 3d network-on-chip. In: Proceedings of the 14th DDECS, pp. 105–110 (April 2011)
Mishra, A.K., et al.: A case for heterogeneous on-chip interconnects for cmps. In: Proceedings of the 38th ISCA, pp. 389–400 (2011)
Zhao, H., et al.: Exploring heterogeneous noc design space. In: Proceedings of the 2011 ICCAD, pp. 787–793 (2011)
Intel: Intel 64 and IA-32 Architectures Optimization Reference Manual. Intel Corporation (2013)
Xu, T.C., et al.: Optimal memory controller placement for chip multiprocessor. In: Proceedings of the 8th CODES+ISSS, pp. 217–226 (October 2011)
Xu, T.C., et al.: A high-efficiency low-cost heterogeneous 3d network-on-chip design. In: Proceedings of the 5th NoCArc, pp. 37–42 (December 2012)
Magnusson, P., et al.: Simics: A full system simulation platform. Computer 35(2), 50–58 (2002)
Martin, M.M., et al.: Multifacet’s general execution-driven multiprocessor simulator (gems) toolset. Computer Architecture News (September 2005)
Woo, S.C., et al.: The splash-2 programs: Characterization and methodological considerations. In: Proceedings of the 22nd ISCA, pp. 24–36 (June 1995)
SPEC: Specjbb 2000, http://www.spec.org/jbb2000/
TPC: Tpc-h decision support benchmark, http://www.tpc.org/tpch/
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Xu, T.C., Liljeberg, P., Plosila, J., Tenhunen, H. (2013). OPTNOC: An Optimized 3D Network-on-Chip Design for Fast Memory Access. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 2013. Lecture Notes in Computer Science, vol 7979. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-39958-9_41
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DOI: https://doi.org/10.1007/978-3-642-39958-9_41
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-39957-2
Online ISBN: 978-3-642-39958-9
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