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MVA-Based Probabilistic Model of Shared Memory with a Round Robin Arbiter for Predicting Performance with Heterogeneous Workload

Conference paper
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Part of the Lecture Notes in Computer Science book series (LNCS, volume 8063)

Abstract

Memory access contention can be a cause of performance problems and should be assessed at early stages of development. We devised a probabilistic model of shared memory for performance estimation. The calculation time is polynomial in the number of processors. The model is applicable for the region of high and heterogeneous bandwidth utilization. A round-robin arbiter is modeled using Mean Value Analysis (MVA) based approximations and incorporating non-linear dependence to the bandwidth utilization. To evaluate our model, estimated execution time is compared with the measured execution time of benchmark programs with memory access contention. We find a maximum error of 4.2% for the round-robin arbitration when we compensate for the burstiness of accesses.

Keywords

embedded system shared memory contention simulation analytic model probabilistic model UML architecture design 

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References

  1. 1.
    Gries, M.: Methods for evaluating and covering the design space during early design development. Integration, the VLSI Journal 38(2), 131–183 (2004)Google Scholar
  2. 2.
    Open SystemC Initiative (OSCI): SystemC specification (2007)Google Scholar
  3. 3.
    Jonkers, H., van Gemund, A., Reijns, G.: A probabilistic approach to parallel system performance modelling. In: Proceedings of the Twenty-Eighth Hawaii International Conference on System Sciences, vol. 2, pp. 412–421 (1995)Google Scholar
  4. 4.
    Cortellessa, V., Pierini, P., Rossi, D.: Integrating software models and platform models for performance analysis. IEEE Transactions on Software Engineering 33(6), 385–401 (2007)CrossRefGoogle Scholar
  5. 5.
    Ono, K., Toyota, M., Kawahara, R., Sakamoto, Y., Nakada, T., Fukuoka, N.: A model-based method for evaluating embedded system performance by abstraction of execution traces. In: Kühne, T., Selic, B., Gervais, M.-P., Terrier, F. (eds.) ECMFA 2010. LNCS, vol. 6138, pp. 233–244. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  6. 6.
    Hoogendoorn, C.H.: A general model for memory interference in multiprocessors. IEEE Transactions on Computers C-26(10), 998–1005 (1977)CrossRefGoogle Scholar
  7. 7.
    Mudge, T.N., Hayes, J.P., Buzzard, G.D., Winsor, D.C.: Analysis of multiple-bus interconnection networks. Journal of Parallel and Distributed Computing 3, 328–343 (1986)CrossRefGoogle Scholar
  8. 8.
    Kawahara, R., Nakamura, K., Ono, K., Nakada, T., Sakamoto, Y.: Coarse-grained simulation method for performance evaluation a of shared memory system. In: Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp. 413–418 (2011)Google Scholar
  9. 9.
    Smilauer, B.: General model for memory interference in multiprocessors and mean value analysis. IEEE Transactions on Computers C-34, 744–751 (1985)CrossRefGoogle Scholar
  10. 10.
    Sorin, D., Lemon, J., Eager, D., Vernon, M.: Analytic evaluation of shared-memory architectures. IEEE Transactions on Parallel and Distributed Systems 14(2), 166–180 (2003)CrossRefGoogle Scholar
  11. 11.
    Bobrek, A., Paul, J.M., Thomas, D.E.: Stochastic contention level simulation for single-chip heterogeneous multiprocessors. IEEE Transactions on Computers 59, 1402–1418 (2010)MathSciNetCrossRefGoogle Scholar
  12. 12.
    Poe, J., Cho, C.B., Li, T.: Using analytical models to efficiently explore hardware transactional memory and multi-core co-design. In: 20th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2008, pp. 159–166 (2008)Google Scholar
  13. 13.
    Darema-Rogers, F., Pfister, G.F., So, K.: Memory access patterns of parallel scientific programs. In: Proceedings of the 1987 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 1987, pp. 46–58. ACM, New York (1987)CrossRefGoogle Scholar
  14. 14.
    Hennessy, J.L., Patterson, D.A.: In: Computer Architecture, 4th edn. A Quantitative Approach, pp. 1–62. Elsevier, Morgan Kaufmann Publishers (2007)Google Scholar
  15. 15.
    Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: Mibench: A free, commercially representative embedded benchmark suite. In: 2001 IEEE International Workshop on Proceedings of the Workload Characterization WWC-4, pp. 3–14. IEEE Computer Society, Washington, DC (2001)Google Scholar
  16. 16.
    Xilinx Inc.: Xilinx ML510 Documentation (2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.IBM Research - TokyoTokyoJapan

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