Advertisement

Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures

  • Marcela Šimková
  • Ondřej Lengál
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7857)

Abstract

Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. In our previous work, we developed HAVEN, an open verification framework that enables hardware acceleration of functional verification runs by moving the design under test (DUT) into a verification environment in a field-programmable gate array (FPGA). In the original version of HAVEN, the generator of input stimuli, the scoreboard and the transfer function still resided in a software simulator, and the peak acceleration ratio achieved was over 1,000. In the currently presented paper, we further extend HAVEN with hardware acceleration of the remaining parts of the verification environment. This enables the user to choose from several different testbed architectures which are evaluated and compared. We show that each architecture provides a different trade-off between the comfort of verification and the degree of acceleration. Using the highest degree of acceleration, we were able to achieve the speed-up in the order of hundreds of thousands while still being able to employ assertion and coverage analysis.

Keywords

Test Vector Acceleration Ratio Cover Point Hardware Acceleration Mersenne Twister 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Šimková, M., Lengál, O.: Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures. Technical Report FIT-TR-2012-03, FIT BUT (2012), http://www.fit.vutbr.cz/~ilengal/pub/FIT-TR-2012-03.pdf
  2. 2.
    Šimková, M., Lengál, O., Kajan, M.: HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware. In: Eder, K., Lourenço, J., Shehory, O. (eds.) HVC 2011. LNCS, vol. 7261, pp. 247–253. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  3. 3.
    Adir, A., Nahir, A., Ziv, A., Meissner, C., Schumann, J.: Reaching Coverage Closure in Post-silicon Validation. In: Barner, S., Kroening, D., Raz, O. (eds.) HVC 2010. LNCS, vol. 6504, pp. 60–75. Springer, Heidelberg (2011)Google Scholar
  4. 4.
    Henftling, R., Zinn, A., Bauer, M., Zambaldi, M., Ecker, W.: Re-Use-Centric Architecture for a Fully Accelerated Testbench Environment. In: Proc. of DAC 2003, pp. 372–375. ACM (2003)Google Scholar
  5. 5.
    Kakoee, M.R., Riazati, M., Mohammadi, S.: Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. In: Proc. of DSD 2008, pp. 714–720. IEEE (2008)Google Scholar
  6. 6.
    Kim, Y.-I., Kyung, C.-M.: Automatic Translation of Behavioral Testbench for Fully Accelerated Simulation. In: Proc. of ICCAD 2004, pp. 218–221. IEEE (2004)Google Scholar
  7. 7.
  8. 8.
    Cadence. Transaction-based Acceleration, TBA (2012), http://www.cadence.com/products/sd/pages/transactionacc.aspx
  9. 9.
    Huang, C.-Y., Yin, Y.-F., Hsu, C.-J., Huang, T.B., Chang, T.M.: SoC HW/SW Verification and Validation. In: Proc. of ASPDAC 2011. IEEE (2011)Google Scholar
  10. 10.
    HT-LAB. Mersenne Twister, MT32: Pseudo Random Number Generator for Xilinx FPGA (2007), http://www.ht-lab.com/freecores/mt32/mersenne.html
  11. 11.

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Marcela Šimková
    • 1
  • Ondřej Lengál
    • 1
  1. 1.Faculty of Information TechnologyBrno University of TechnologyCzech Republic

Personalised recommendations