A Novel Approach for Implementing Microarchitectural Verification Plans in Processor Designs

  • Yoav Katz
  • Michal Rimon
  • Avi Ziv
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7857)


The ever-growing microarchitecture complexity of processors creates a widening gap between the verification plan and the test generation technologies used in its implementation. This gap impacts the cost and quality of the verification process. To overcome this, we introduce a novel test generation platform for processor verification. This approach is based on a scenario description language that is close to the microarchitecture verification plan, and uses new test generation algorithms and a microarchitectural model to support this higher level of abstraction. Initial results on a high end industrial design show our approach reduces the effort of implementing a microarchitectural verification plan and improves the quality of verification.


Test Generation Constraint Satisfaction Problem Testing Knowledge Cache Line Inductive Logic Programming 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Wile, B., Goss, J.C., Roesner, W.: Comprehensive Functional Verification - The Complete Industry Cycle. Elsevier (2005)Google Scholar
  2. 2.
    Adir, A., Almog, E., Fournier, L., Marcus, E., Rimon, M., Vinov, M., Ziv, A.: Genesys-Pro: Innovations in test program generation for functional processor verification. IEEE Design and Test of Computers 21(2), 84–93 (2004)CrossRefGoogle Scholar
  3. 3.
    Hennenhoefer, E., Typaldos, M.: The evolution of processor test generation technology,
  4. 4.
    Naveh, Y., Rimon, M., Jaeger, I., Katz, Y., Vinov, M., Marcus, E., Shurek, G.: Constraint-based random stimuli generation for hardware verification. AI Magazine 28(3), 13–30 (2007)Google Scholar
  5. 5.
    Ludden, J.M., Rimon, M., Hickerson, B.G., Adir, A.: Advances in simultaneous multithreading testcase generation methods. In: Barner, S., Kroening, D., Raz, O. (eds.) HVC 2010. LNCS, vol. 6504, pp. 146–160. Springer, Heidelberg (2011)Google Scholar
  6. 6.
    Burns, D.: Pre-silicon validation of hyper-threading technology. Intel Technology Journal 6(1) (2002)Google Scholar
  7. 7.
    Adir, A., Bin, E., Ziv, A.: Piparazzi: A test generator for micro-architecture flow verification. In: Proceedings of the High-Level Design Validation and Test Workshop, pp. 23–28 (2003)Google Scholar
  8. 8.
    Mishra, P., Dutt, N.: Specification-driven directed test generation for validation of pipelined processors. ACM Trans. Design Autom. Electr. Syst. 13(3) (2008)Google Scholar
  9. 9.
    Fine, S., Ziv, A.: Coverage directed test generation for functional verification using Bayesian networks. In: Proceedings of the 40th Design Automation Conference, pp. 286–291 (2003)Google Scholar
  10. 10.
    Squillero, G.: MicroGP—an evolutionary assembly program generator. Genetic Programming and Evolvable Machines 6(3), 247–263 (2005)CrossRefGoogle Scholar
  11. 11.
    Wagner, I., Bertacco, V., Austin, T.: Microprocessor verification via feedback-adjusted Markov models. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(6), 1126–1138 (2007)CrossRefGoogle Scholar
  12. 12.
    Eder, K., Flach, P., Hsueh, H.-W.: Towards automating simulation-based design verification using ILP. In: Muggleton, S., Otero, R., Tamaddoni-Nezhad, A. (eds.) ILP 2006. LNCS (LNAI), vol. 4455, pp. 154–168. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  13. 13.
    Ioannides, C., Barrett, G., Eder, K.: Feedback-based coverage directed test generation: An industrial evaluation. In: Barner, S., Kroening, D., Raz, O. (eds.) HVC 2010. LNCS, vol. 6504, pp. 112–128. Springer, Heidelberg (2011)Google Scholar
  14. 14.
    Katz, Y., Rimon, M., Ziv, A., Shaked, G.: Learning microarchitectural behaviors to improve stimuli generation quality. In: Proceedings of the 48th Design Automation Conference, pp. 848–853 (2011)Google Scholar
  15. 15.
    Katz, Y., Rimon, M., Ziv, A.: Generating instruction streams using abstract CSP. In: Proceedings of the 2012 Design, Automation and Test in Europe Conference, pp. 15–20 (2012)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Yoav Katz
    • 1
  • Michal Rimon
    • 2
  • Avi Ziv
    • 1
  1. 1.IBM Research - HaifaIsrael
  2. 2.IBM Server and Technology GroupHaifaIsrael

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