Hardware Architectures for MSP430-Based Wireless Sensor Nodes Performing Elliptic Curve Cryptography

  • Erich Wenger
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7954)


Maximizing the battery lifetime of wireless sensor nodes and equipping them with elliptic curve cryptography is a challenge that requires new energy-saving architectures. In this paper, we present an architecture that drops a hardware accelerator between CPU and RAM. Thus neither the CPU nor the data memory need to be modified. In a detailed comparison with a software-only and a dedicated hardware architecture, we show that the drop-in concept is smaller than the dedicated hardware module, while achieving similarly fast runtimes. Most interesting for micro-chip manufacturers is that only 4 kGE of chip area need to be committed for the dedicated drop-in accelerator.


MSP430 ASIC Hardware Software Elliptic Curve Cryptography Wireless Sensor Nodes 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Erich Wenger
    • 1
  1. 1.Institute for Applied Information Processing and CommunicationsGraz University of TechnologyGrazAustria

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