Abstract
In this paper we present a method to estimate the scheduling discipline applied on the output port on an Ethernet switch. We use well known formulas to calculate the expected output rate of a scheduler. Assuming that it is one of the following scheduling algorithms FIFO, Fixed Priority or Round Robin, we measure the actual output bandwidth and find the most likely scheduling algorithm. We present both a simulation study and a practical implementation where the proposed principle is implemented on a FPGA based high-pression Ethernet testbed.
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Revsbech, K., Madsen, T.K., Schiøler, H. (2013). Estimating the Scheduling Discipline of an Ethernet Switch Using Constant Bit-Rate Probes. In: Berbineau, M., et al. Communication Technologies for Vehicles. Nets4Cars/Nets4Trains 2013. Lecture Notes in Computer Science, vol 7865. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-37974-1_13
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DOI: https://doi.org/10.1007/978-3-642-37974-1_13
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-37973-4
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