Abstract
Memory latency and energy efficiency are two key constraints to high performance computing systems. Data reuse transformations aim at reducing memory latency by exploiting temporal locality in data accesses. Simultaneously, modern multicore processors provide the opportunity of improving performance with reduced energy dissipation through parallelization. In this paper, we investigate to what extent data reuse transformations in combination with a parallel programming model in a multicore processor can meet the challenges of memory latency and energy efficiency constraints. As a test case, a “full-search motion estimation” kernel is run on the Intel® CoreTM i7-2600 processor. Energy Delay Product (EDP) is used as a metric to compare energy efficiencies. Achieved results show that performance and energy efficiency can be improved by a factor of more than 6 and 15, respectively, by exploiting a data reuse transformation methodology and parallel programming model in a multicore system.
Keywords
- Performance
- energy efficiency
- data reuse transformation methodology
- parallel programming
Download conference paper PDF
References
Albers, S.: Energy-Efficient Algorithms. Communications of the ACM 53(5), 86–96 (2011)
Wuytack, S., Diguet, J.P., Catthoor, F., et al.: Formalized Methodology for Data Reuse Exploration for Low-Power Hierarchical Memory Mappings. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6(4), 529–537 (1998)
Catthoor, F., Danckaert, K., Kulkarni, K., et al.: Data Access and Storage Management for Embedded Programmable Processors. Kluwer Academic Publishers, Dordrecht (2002)
Catthoor, F., Wuytack, S., de Greef, G., et al.: Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design. Kluwer Academic Publishers, Norwell (1998)
Zervas, N.D., Masselos, K., Goutis, C.E.: Data-Reuse Exploration for Low-Power Realization of Multimedia Applications on Embedded Cores. In: Proc. 9th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 1999, pp. 71–80 (1999)
Chatzigeorgiou, A., Chatzigeorgiou, E., Kougia, S., et al.: Evaluating the Effect of Data-Reuse Transformations on Processor Power Consumption (2001)
Vassiliadis, N., Chormoviti, A., Kavvadias, N., et al.: The Effect of Data-Reuse Transformations on Multimedia Applications for Application Specific Processors. In: Proc. Intelligent Data Acquisition and Advanced Computing Systems Technology and Applications, IDAACS 2005, pp. 179–182 (September 2005)
Kalva, H., Colic, A., Garcia, A., et al.: Parallel Programming for Multimedia Applications. Multimedia Tools and Applications 51(2), 801–818 (2011)
Chen, L., Hu, Z., Lin, J., et al.: Optimizing the Fast Fourier Transform on a Multi-core Architectures. In: Proc. Parallel and Distributed Processing Symposium, IPDPS 2007, pp. 1–8 (March 2007)
Zhang, Y., Kandemir, M., Yemliha, T.: Studying Inter-core Data Reuse in Multicores. In: Proc. ACM SIGMETRICS Joint International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2011, pp. 25–36 (2011)
Marchal, P., Catthoor, F., Bruni, D., et al.: Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications. IEEE Design & Test of Computers 21(5), 378–387 (2004)
Podobas, A., Brorsson, M., Faxén, K.F.: A Comparison of some recent Task-based Parallel Programming Models. In: Proc. 3rd Workshop on Programmability Issues for Multi-Core Computers, Pisa, Italy (January 2010)
OpenMP Architecture Review Board: OpenMP Application Program Interface (July 2011), http://www.openmp.org/mp-documents/OpenMP3.1.pdf
Komarek, T., Pirsch, P.: Array Architectures for Block Matching Algorithms. IEEE Transactions on Circuits and Systems 36(10), 1301–1308 (1989)
Intel: Intel 64 and IA-32 Architectures Software Developer’s Manual (2011)
Rivoire, S., Shah, M.A., Ranganathan, P., et al.: Models and Metrics to Enable Energy-Efficiency Optimizations. Computer 40(12), 39–48 (2007)
Flautner, K., Kim, N.S., Martin, S., et al.: Drowsy Caches: Simple Techniques for Reducing Leakage Power. In: Proc. 29th Annual International Symposium on Computer Architecture, ISCA 2002, Washington, DC, USA, pp. 148–157 (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Hasib, A.A., Kjeldsberg, P.G., Natvig, L. (2013). Performance and Energy Efficiency Analysis of Data Reuse Transformation Methodology on Multicore Processor. In: , et al. Euro-Par 2012: Parallel Processing Workshops. Euro-Par 2012. Lecture Notes in Computer Science, vol 7640. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36949-0_37
Download citation
DOI: https://doi.org/10.1007/978-3-642-36949-0_37
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-36948-3
Online ISBN: 978-3-642-36949-0
eBook Packages: Computer ScienceComputer Science (R0)