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Speed Optimization Using Tri-state Output Buffers

  • Robert Czerwinski
  • Dariusz Kania
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 231)

Abstract

The idea of speed optimization is presented in the chapter. The main restriction of PAL-based logic cells is a relatively low number of terms. It does not allow implementation of every function within the single PAL-based cell. Thus, additional term expansion is necessary. The classical expansion enables implementation of every function, but significantly “slower” solutions are obtained. A typical PAL-based cell usually includes a tri-state output buffer. The presented method of speed optimization dedicated for programmable PAL-based devices containing tristate output buffers leads to implementation of digital circuits in the form of onecell- level structures.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Institute of ElectronicsSilesian University of TechnologyGliwicePoland

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