Speed Optimization Using Tri-state Output Buffers
The idea of speed optimization is presented in the chapter. The main restriction of PAL-based logic cells is a relatively low number of terms. It does not allow implementation of every function within the single PAL-based cell. Thus, additional term expansion is necessary. The classical expansion enables implementation of every function, but significantly “slower” solutions are obtained. A typical PAL-based cell usually includes a tri-state output buffer. The presented method of speed optimization dedicated for programmable PAL-based devices containing tristate output buffers leads to implementation of digital circuits in the form of onecell- level structures.
Unable to display preview. Download preview PDF.
- 3.De Micheli, G.: Synthesis and optimization of digital circuits. McGraw-Hill Inc. (1994)Google Scholar
- 4.Kania, D.: Two-level logic synthesis on PAL-based CPLD and FPGA using decomposition. In: Proceedings of 25th Euromicro Conference, pp. 278–281. IEEE Computer Society Press, Milan (1999)Google Scholar
- 6.Kania, D.: Decomposition-based synthesis and its application in PAL-oriented technology mapping. In: Proceedings of 26th Euromicro Conference, pp. 138–145. IEEE Computer Society Press, Maastricht (2000)Google Scholar
- 7.Kania, D.: The logic synthesis for the PAL-based CPLDs. Silesian University of Technology, Gliwice (2004) (in Polish)Google Scholar
- 8.Kania, D.: A p-stage logic synthesis for PAL-based devices. Electronics and Telecommunications Quarterly 1(50), 65–86 (2004) (in Polish) Google Scholar
- 10.MCNC, LGSynth’91 benchmarks. Collaborative Benchmarking Laboratory, Department of Computer Science at North Carolina State University (1991), http://www.cbl.ncsu.edu:16080/benchmarks/LGSynth91/