Abstract
To efficiently maintain cache coherence in a many-core processor remains a big challenge today. Traditional protocols either offer low cache miss latency (like snoopy protocol) or not depending on bus-like interconnects (like directory protocol). Recently, Token Coherence has been proposed to capture the main characteristic of traditional protocols. However, since Token Coherence relies on broadcast-based transient request and inefficient persistent request, it is only suitable for small system. In order to make Token Coherence be scalable in many-core architectures, in this paper we introduce a dynamically reconfigurable mechanism to Token Coherence. Basing on sub-net, this mechanism can significantly reduce the average execution time and communication cost in 16-core processor. Therefore, this dynamically reconfigurable mechanism makes Token Coherence applicable in many-core architecture.
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Zhou, C., Fu, Y., Jiang, J., Han, X., Yang, K. (2013). Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Processor. In: Xu, W., Xiao, L., Lu, P., Li, J., Zhang, C. (eds) Computer Engineering and Technology. NCCET 2012. Communications in Computer and Information Science, vol 337. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35898-2_6
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DOI: https://doi.org/10.1007/978-3-642-35898-2_6
Publisher Name: Springer, Berlin, Heidelberg
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