Real-Time Runtime Verification on Chip

  • Thomas Reinbacher
  • Matthias Függer
  • Jörg Brauer
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7687)


We present an algorithmic framework that allows on-line monitoring of past-time MTL specifications in a discrete time setting. The algorithms allow to be synthesized into efficient observer hardware blocks, which take advantage of the highly-parallel nature of hardware designs. For the time-bounded Since operator of past-time MTL we obtain a time complexity that is double logarithmic in the time it is executed at and the given time bounds of the Since operator. This result is promising with respect to a non-interfering monitoring approach that evaluates real-time specifications during the execution of the system-under-test. The resulting hardware blocks are reconfigurable and have applications in prototyping and runtime verification of embedded real-time systems.


Temporal Logic Space Complexity Garbage Collection Parse Tree Atomic Proposition 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Alur, R., Henzinger, T.A.: Real-time Logics: Complexity and Expressiveness. In: LICS, pp. 390–401. IEEE (1990)Google Scholar
  2. 2.
    Baier, C., Katoen, J.P.: Principles of Model Checking. The MIT Press (2008)Google Scholar
  3. 3.
    Barringer, H., Falcone, Y., Finkbeiner, B., Havelund, K., Lee, I., Pace, G., Roşu, G., Sokolsky, O., Tillmann, N. (eds.): RV 2010. LNCS, vol. 6418. Springer, Heidelberg (2010)Google Scholar
  4. 4.
    Basin, D., Klaedtke, F., Zălinescu, E.: Algorithms for Monitoring Real-Time Properties. In: Khurshid, S., Sen, K. (eds.) RV 2011. LNCS, vol. 7186, pp. 260–275. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  5. 5.
    Borrione, D., Liu, M., Morin-Allory, K., Ostier, P., Fesquet, L.: On-line assertion-based verification with proven correct monitors. In: ICICT, pp. 125–143 (2005)Google Scholar
  6. 6.
    Boulé, M., Zilic, Z.: Automata-based assertion-checker synthesis of PSL properties. ACM Transactions on Design Automation of Electronic Systems 13(1) (2008)Google Scholar
  7. 7.
    Colombo, C., Pace, G.J., Schneider, G.: Safe Runtime Verification of Real-Time Properties. In: Ouaknine, J., Vaandrager, F.W. (eds.) FORMATS 2009. LNCS, vol. 5813, pp. 103–117. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  8. 8.
    Das, S., Mohanty, R., Dasgupta, P., Chakrabarti, P.: Synthesis of system verilog assertions. In: DATE, vol. 2, pp. 1–6 (2006)Google Scholar
  9. 9.
    Divakaran, S., D’Souza, D., Mohan, M.R.: Conflict-tolerant real-time specifications in metric temporal logic. In: TIME, pp. 35–42 (2010)Google Scholar
  10. 10.
    Emerson, E.A.: Temporal and modal logic. In: Handbook of Theoretical Computer Science, vol. B, pp. 995–1072. MIT Press (1990)Google Scholar
  11. 11.
    Fischmeister, S., Lam, P.: Time-aware instrumentation of embedded software. IEEE Transactions on Industrial Informatics 6(4), 652–663 (2010)CrossRefGoogle Scholar
  12. 12.
    Havelund, K., Roşu, G.: An overview of the runtime verification tool Java PathExplorer. Formal Methods in System Design 24(2), 189–215 (2004)zbMATHCrossRefGoogle Scholar
  13. 13.
    Havelund, K., Roşu, G.: Efficient monitoring of safety properties. International Journal on Software Tools for Technology Transfer 6, 158–173 (2004)CrossRefGoogle Scholar
  14. 14.
    Hopcroft, J.E., Motwani, R., Ullman, J.D.: Introduction to Automata Theory, Languages, and Computation. Addison-Wesley Longman Publishing Co., Inc. (2006)Google Scholar
  15. 15.
    Kogge, P.M., Stone, H.S.: A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Trans. Comput. 22(8), 786–793 (1973)MathSciNetzbMATHCrossRefGoogle Scholar
  16. 16.
    Latvala, T., Biere, A., Heljanko, K., Junttila, T.A.: Simple Is Better: Efficient Bounded Model Checking for Past LTL. In: Cousot, R. (ed.) VMCAI 2005. LNCS, vol. 3385, pp. 380–395. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  17. 17.
    Lee, I., Kannan, S., Kim, M., Sokolsky, O., Viswanathan, M.: Runtime assurance based on formal specifications. In: PDPTA, pp. 279–287 (1999)Google Scholar
  18. 18.
    Lichtenstein, O., Pnueli, A., Zuck, L.: The Glory of the Past. In: Parikh, R. (ed.) Logic of Programs 1985. LNCS, vol. 193, pp. 196–218. Springer, Heidelberg (1985)CrossRefGoogle Scholar
  19. 19.
    Maler, O., Nickovic, D., Pnueli, A.: Real Time Temporal Logic: Past, Present, Future. In: Pettersson, P., Yi, W. (eds.) FORMATS 2005. LNCS, vol. 3829, pp. 2–16. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  20. 20.
    Manna, Z., Pnueli, A.: The temporal logic of reactive and concurrent systems. Springer (1992)Google Scholar
  21. 21.
    Morin-Allory, K., Borrione, D.: Proven correct monitors from PSL specifications. In: DATE, pp. 1–6 (2006)Google Scholar
  22. 22.
    Pellizzoni, R., Meredith, P., Caccamo, M., Rosu, G.: Hardware runtime monitoring for dependable COTS-based real-time embedded systems. In: RTSS, pp. 481–491 (2008)Google Scholar
  23. 23.
    Pike, L., Niller, S., Wegmann, N.: Runtime Verification for Ultra-Critical Systems. In: Khurshid, S., Sen, K. (eds.) RV 2011. LNCS, vol. 7186, pp. 310–324. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  24. 24.
    Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., Kowalewski, S.: Past Time LTL Runtime Verification for Microcontroller Binary Code. In: Salaün, G., Schätz, B. (eds.) FMICS 2011. LNCS, vol. 6959, pp. 37–51. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  25. 25.
    Thati, P., Roşu, G.: Monitoring Algorithms for Metric Temporal Logic specifications. ENTCS 113, 145–162 (2005)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Thomas Reinbacher
    • 1
  • Matthias Függer
    • 1
  • Jörg Brauer
    • 2
    • 3
  1. 1.Embedded Computing Systems GroupVienna University of TechnologyAustria
  2. 2.Verified Systems International GmbHBremenGermany
  3. 3.Embedded Software LaboratoryRWTH Aachen UniversityGermany

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