Abstract
Reversible logic is becoming one of the emerging technologies because of its applications in low power design, quantum computing, quantum dot cellular automata and optical computing. As a result, design of reversible logic computing has been gaining more and more attention from researchers, since, under ideal physical circumstances the power dissipation of reversible computing is zero. Conventional decoder and encoder circuits which found applications in memories, processors, communications etc., are power inefficient. In this work, a decoder, encoder and priority encoder are realized using reversible logic to reduce power dissipation. A reversible linear feedback shift register and multiple input signature register are designed to facilitate built – in self-test based on signature analysis. The proposed circuits are tested for single stuck-at, single missing gate and multiple missing gate faults.
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© 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
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Syamala, Y., Tilak, A.V.N., Srilakshmi, K. (2012). Testing of Reversible Combinational Circuits. In: Das, V.V., Stephen, J. (eds) Advances in Communication, Network, and Computing. CNC 2012. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 108. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35615-5_7
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DOI: https://doi.org/10.1007/978-3-642-35615-5_7
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