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IFIP International Conference on Network and Parallel Computing

NPC 2012: Network and Parallel Computing pp 33–41Cite as

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Communication Locality Analysis of Triplet-Based Hierarchical Interconnection Network in Chip Multiprocessor

Communication Locality Analysis of Triplet-Based Hierarchical Interconnection Network in Chip Multiprocessor

  • Shahnawaz Talpur20,21,
  • Feng Shi20 &
  • Yizhuo Wang20 
  • Conference paper
  • 2272 Accesses

Part of the Lecture Notes in Computer Science book series (LNTCS,volume 7513)

Abstract

Interconnection topology inside chip multiprocessor acts as fundamental role in communication locality. Considering compiler optimization data locality has been an inmost hypothesis in the high performance computing. Conversely, data locality sphere has several troubles when its degree of dimension is two or higher. In mesh network of two dimensions, each core is connected with its four neighbors. The data locality can potentially be exploited in two dimensions considering the specified processor’s perspective. A Triplet-Based Hierarchical Interconnection Network (TBHIN) has straightforward topology and fractal attribute for chip multiprocessor. In this paper, a static (no contention) performance analysis of TBHIN and 2-D mesh is presented, based on the premise of locality in communication. The dynamic (contention) software simulation of TBHIN shows that the stronger the locality in communication, the lower the delay of the communication.

Keywords

  • Chip multiprocessor
  • communication locality
  • interconnection network
  • mesh

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Author information

Authors and Affiliations

  1. Beijing Institute of Technology, Beijing, P.R. China

    Shahnawaz Talpur, Feng Shi & Yizhuo Wang

  2. Department of Computer Systems Engineering, Mehran University of Engineering & Technology Jamshoro, Sindh, Pakistan

    Shahnawaz Talpur

Authors
  1. Shahnawaz Talpur
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  2. Feng Shi
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  3. Yizhuo Wang
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Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, SeoulTech, 172 Gongreung 2-dong, Nowon-gu, 139-743, Seoul, Korea

    James J. Park

  2. School of Information Technologies, The University of Sydney, Building J12, 2006, Sydney, NSW, Australia

    Albert Zomaya

  3. Division of Computer Engineering, Mokwon University, 88 Do-An-Buk-Ro, Seo-gu, 302-729, Daejeon, Korea

    Sang-Soo Yeo

  4. Department of Computer and Information Science and Engineering, University of Florida, CSE 301, 32611, Gainesville, FL, USA

    Sartaj Sahni

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© 2012 IFIP International Federation for Information Processing

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Cite this paper

Talpur, S., Shi, F., Wang, Y. (2012). Communication Locality Analysis of Triplet-Based Hierarchical Interconnection Network in Chip Multiprocessor. In: Park, J.J., Zomaya, A., Yeo, SS., Sahni, S. (eds) Network and Parallel Computing. NPC 2012. Lecture Notes in Computer Science, vol 7513. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35606-3_4

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  • DOI: https://doi.org/10.1007/978-3-642-35606-3_4

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