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High Speed LDPC Encoder Architecture for Digital Video Broadcasting Systems

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Computer Applications for Database, Education, and Ubiquitous Computing (EL 2012, DTA 2012)

Abstract

In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.

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References

  1. Gallager, R.G.: Low-Density Parity-Check Codes. IRE Trans. Infom. Theory IT-8, 21–28 (1962)

    Article  MathSciNet  Google Scholar 

  2. Eroz, M., Sun, F.W., Lee, L.N.: DVB-S2 low density parity check codes with near Shannon limit performance. Int. J. Satell. Commun. Network 22(3), 269–279 (2004)

    Article  Google Scholar 

  3. Urad, P., Yeo, E., Paumier, L., Georgelin, P., Michel, T., Lebars, V., Yeo, E., Gupta, B.: A 135Mb/s DVB-S2 Compliant CODEC based on 64800b LDPC and BCH Codes. In: Proc. ISSCC 2005, San Francisco, USA, pp. 446–447 (February 2005)

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  4. Kienle, F., Brack, T., Wehn, N.: A synthesizable IP core for DVB-S2 LDPC code decoding. In: Proc. Design, Automation and Test in Europe 2005, vol. 3, pp. 100–105 (March 2005)

    Google Scholar 

  5. Yokokawa, T., Nakane, M., Kan, M.: A Low Complexity and Programmable Encoder Architecture of the LDPC codes for DVB-S2. In: 3rd Turbo Coding Conference, Munich, Germany, (April 2006)

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© 2012 Springer-Verlag Berlin Heidelberg

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Jung, J.W., Park, G.Y. (2012). High Speed LDPC Encoder Architecture for Digital Video Broadcasting Systems. In: Kim, Th., Ma, J., Fang, Wc., Zhang, Y., Cuzzocrea, A. (eds) Computer Applications for Database, Education, and Ubiquitous Computing. EL DTA 2012 2012. Communications in Computer and Information Science, vol 352. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35603-2_34

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  • DOI: https://doi.org/10.1007/978-3-642-35603-2_34

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-35602-5

  • Online ISBN: 978-3-642-35603-2

  • eBook Packages: Computer ScienceComputer Science (R0)

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