Abstract
In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.
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© 2012 Springer-Verlag Berlin Heidelberg
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Jung, J.W., Park, G.Y. (2012). High Speed LDPC Encoder Architecture for Digital Video Broadcasting Systems. In: Kim, Th., Ma, J., Fang, Wc., Zhang, Y., Cuzzocrea, A. (eds) Computer Applications for Database, Education, and Ubiquitous Computing. EL DTA 2012 2012. Communications in Computer and Information Science, vol 352. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35603-2_34
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DOI: https://doi.org/10.1007/978-3-642-35603-2_34
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-35602-5
Online ISBN: 978-3-642-35603-2
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