Performance Evaluation of the Sector Mapping Schemes Considering Mapping Table Size
The goal of the paper is to evaluate the performance of the sector mapping schems of flash translation layer (FTL) considering the different memory requirements of the schemes. Under the given memory, we assume that the available memory space is used as buffer for NAND flash memory and that the buffer is managed by the block-level LRU replacement scheme. The trace-drive simulation shows that the page mapping scheme delivers the best performance even though the available buffer size is smaller than other schemes. However, in the very memory-hash environment, other hybrid mapping schemes delivers a better performance than the page mapping scheme.
Keywordsflash translation layer NAND flash memory memory requirement buffer
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