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On the Correctness of an Optimising Assembler for the Intel MCS-51 Microprocessor

  • Conference paper

Part of the Lecture Notes in Computer Science book series (LNTCS,volume 7679)

Abstract

We present a proof of correctness in Matita for an optimising assembler for the MCS-51 microcontroller. The efficient expansion of pseudoinstructions, namely jumps, into machine instructions is complex. We isolate the decision making over how jumps should be expanded from the expansion process itself as much as possible using ‘policies’, making the proof of correctness for the assembler more straightforward.

Our proof strategy contains a tracking facility for ‘good addresses’ and only programs that use good addresses have their semantics preserved under assembly, as we observe that it is impossible for an assembler to preserve the semantics of every assembly program. Our strategy offers increased flexibility over the traditional approach to proving the correctness of assemblers, wherein addresses in assembly are kept opaque and immutable. In particular, we may experiment with allowing the benign manipulation of addresses.

Keywords

  • Verified software
  • CerCo (Certified Complexity)
  • MCS-51 microcontroller
  • Matita proof assistant

The project CerCo acknowledges the financial support of the Future and Emerging Technologies (FET) programme within the Seventh Framework Programme for Research of the European Commission, under FET-Open grant number: 243881.

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References

  1. Asperti, A., Sacerdoti Coen, C., Tassi, E., Zacchiroli, S.: User interaction with the Matita proof assistant. Automated Reasoning 39, 109–139 (2007)

    CrossRef  MATH  Google Scholar 

  2. Boender, J., Sacerdoti Coen, C.: On the correctness of a branch displacement algorithm (2012), http://arxiv.org/abs/1209.5920

  3. The CerCo FET-Open project (2011), http://cerco.cs.unibo.it/

  4. Branch displacement optimisation (2006), http://groups.google.com/group/alt.lang.asm/msg/d31192d442accad3

  5. Klein, G., Andronick, J., Elphinstone, K., Heiser, G., Cock, D., Derrin, P., Elkaduwe, D., Engelhardt, K., Kolanski, R., Norrish, M., Sewell, T., Tuch, H., Winwood, S.: seL4: Formal verification of an operating system kernel. In: SOSP (2009)

    Google Scholar 

  6. Klein, G., Nipkow, T.: A machine-checked model for a Java-like language, virtual machine and compiler. ACM Transactions on Programming Languages and Systems 28(4), 619–695 (2006)

    CrossRef  Google Scholar 

  7. Leroy, X.: A formally verified compiler back-end. Automated Reasoning 43(4), 363–446 (2009)

    CrossRef  MathSciNet  MATH  Google Scholar 

  8. Moore, J.S.: Piton: A mechanically verified assembly language. Automated Reasoning Series, vol. 3. Springer (1996)

    Google Scholar 

  9. Moore, J.S.: A grand challenge proposal for formal methods (2005)

    Google Scholar 

  10. Small device C compiler 3.0.0 (2011), http://sdcc.sourceforge.net/

  11. Siemens Semiconductor Group 8051 derivative instruction set (2011), http://www.win.tue.nl/~aeb/comp/8051/instruction-set.pdf

  12. Sozeau, M.: Subset Coercions in Coq. In: Altenkirch, T., McBride, C. (eds.) TYPES 2006. LNCS, vol. 4502, pp. 237–252. Springer, Heidelberg (2007)

    CrossRef  Google Scholar 

  13. Tuch, H., Klein, G., Norrish, M.: Types, bytes, and separation logic. In: POPL, pp. 97–108 (2007)

    Google Scholar 

  14. Ševčík, J., Vafeiadis, V., Zappa Nardelli, F., Jagannathan, S., Sewell, P.: Relaxed-memory concurrency and verified compilation. In: POPL, pp. 43–54 (2011)

    Google Scholar 

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Mulligan, D.P., Sacerdoti Coen, C. (2012). On the Correctness of an Optimising Assembler for the Intel MCS-51 Microprocessor. In: Hawblitzel, C., Miller, D. (eds) Certified Programs and Proofs. CPP 2012. Lecture Notes in Computer Science, vol 7679. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35308-6_7

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  • DOI: https://doi.org/10.1007/978-3-642-35308-6_7

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-35307-9

  • Online ISBN: 978-3-642-35308-6

  • eBook Packages: Computer ScienceComputer Science (R0)