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Delta-Sigma A/D-Converters pp 55–73Cite as

A Delta-Sigma Converter with Dynamic-Biasing Technique

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Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 39))

Abstract

A high-resolution multi-bit Delta-Sigma ADC implemented in a 0.18 μm CMOS technology is introduced [47]. The circuit is targeted for an ADSL Central-Office application. An area- and power-efficient realization of a single-loop modulator consisting of a 2nd-order loopfilter and a 3-bit quantizer with an oversampling-ratio of 96 is presented. The delta-sigma modulator features an 85 dB dynamic-range (DR) over a 300 kHz signal bandwidth. The measured power consumption of the ADC core is 15 mW only. An innovative biasing circuitry is introduced for the switched-capacitor integrators. The FOM taking the DR as reference (2.7) results in \(1.8~\frac{\mathrm{pJ}}{\mathrm{conv}}\).

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Notes

  1. 1.

    Note, for the given bandwidth of 300 kHz a reasonably high GBW can be afforded in the provided technology.

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Authors and Affiliations

  1. Design Center Villach, Infineon Technologies, Villach, Austria

    Richard Gaggl

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  1. Richard Gaggl
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Gaggl, R. (2013). A Delta-Sigma Converter with Dynamic-Biasing Technique. In: Delta-Sigma A/D-Converters. Springer Series in Advanced Microelectronics, vol 39. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-34543-2_3

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  • DOI: https://doi.org/10.1007/978-3-642-34543-2_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-34542-5

  • Online ISBN: 978-3-642-34543-2

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