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Study on Rasterization Algorithm for Graphics Acceleration System

  • Xuzhi Wang
  • Wei Xiong
  • Xiang Feng
  • Shuai Yu
  • Hengyong Jiang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7667)

Abstract

The 3D devices have been widely applied in people’s life, for example, smart phone, internet games, high-definition video, geography navigation, etc. The large scale graphics rendering depends on the computing power of the hardware greatly, the calculation of model rasterization operations need amounts of data. It has become the bottleneck of system performance. This paper proposed the method which can accelerate graphics rasterization procedure, based on the idea of tile to meet the needs of graphical applications on embedded platform. The rules and procedures of algorithm are introduced. By using of the XUP-LX110T, the experiments are carried out. It is verified that the method should been compensated the features for the lack of resources and poor computing power of embedded platforms. It can apply smaller chip area to achieve graphics acceleration with fewer resources.

Keywords

Rasterization Tile rendering FPGA Block_edge_test (HET) 

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References

  1. 1.
    Hans, H.: Embedded 3D Graphics Core for FPGA-based System-on-chip Applications. In: FPGA World Conference, pp. 8–13 (2005)Google Scholar
  2. 2.
    Fredrik, E.: A Tile-based Triangle Rasterizer in Hardware (2009) Google Scholar
  3. 3.
    Kim, D., Kim, L.: Area Efficient Pixel Rasterization and Texture Coordinate Interpolation. Comput. Graphics (2008) Google Scholar
  4. 4.
    Juan, P.: A Parallel Algorithm for Polygon Rasterization. In: Proceedings of the 15th Annual Conference on Computer Graphics and Interactive Techniques, pp. 17–20 (1988)Google Scholar
  5. 5.
    Michael, D.M., Chris, W., Kevin, M.: Incremental and Hierarchical Hilbert Order Edge Equation Polygon Rasterization. In: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, pp. 65–72 (2001)Google Scholar
  6. 6.
    Oberman, S.F., Siu, M.Y.: A High Performance Area Efficient Multifunction Interpolator. In: Symposium on Computer Arithmetic, pp. 272–275 (2005)Google Scholar
  7. 7.
    Voicu, P., Paul, R.: Forward Rasterization. ACM Trans. Graph. 62, 375–411 (2006)Google Scholar
  8. 8.
    Kyusik, C., Kim, D., Kim, L.: A 3-way SIMD Engine for Programmable Triangle Setup in Embedded 3D Graphics Hardware. In: IEEE International Symposium on Circuits and Systems, pp. 4546–4549. IEEE Press, New York (2005)CrossRefGoogle Scholar
  9. 9.
    Tomas, A.: Fast 3D Triangle-Box Overlap Testing. In: SIGGRAPH 2005 ACM SIGGRAPH 2005 Courses, pp. 1–4. ACM, New York (2005)Google Scholar
  10. 10.
    Steven, M.: A Sorting Classification of Parallel Rendering. In: ACM SIGGRAPH ASIA 2008 Courses. ACM, New York (2008)Google Scholar
  11. 11.
    Joel, M., Robert, M.: Tiled Polygon Traversal Using Half-plane Edge Functions. In: Proceedings of the ACM SIGGRAPH EUROGRAPHICS Workshop on Graphics Hardware, pp. 15–21. ACM, New York (2000)Google Scholar
  12. 12.
    Nguyen, H.T.: An Efficient Data-Parallel Architecture for Volume Rendering. In: IEEE Region 10’s Ninth Annual International Conference, pp. 664–671. IEEE Press, New York (1994)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Xuzhi Wang
    • 1
  • Wei Xiong
    • 1
  • Xiang Feng
    • 1
  • Shuai Yu
    • 1
  • Hengyong Jiang
    • 1
  1. 1.School of Communication and Information EngineeringShanghai UniversityShanghaiChina

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