A Novel Circuit Design Methodology to Reduce Side Channel Leakage

  • Andreas Gornik
  • Ivan Stoychev
  • Jürgen Oehm
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7644)


To estimate the probable information leakage of a logic circuit through a side channel is a major problem for circuit designers. In this paper a novel circuit design methodology is presented to estimate and reduce the side channel leakage of logic gates. The focus lies on the investigation of side channel leakage during circuit design. With this novel methodology three different logic circuit families are compared. Additionally, the process of improving a logic circuit using this methodology is shown in detail.


circuit design DPA countermeasures side channel leakage 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  2. 2.
    Schneider, O., Uffmann, D.: Circuit Configuration for Generating Current Pulses in the Supply Current of Integrated Circuits. US Patent US 7, 017, 048 B2 (March 2006)Google Scholar
  3. 3.
    Shamir, A.: Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 71–77. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  4. 4.
    Medwed, M., Standaert, F.-X., Großschädl, J., Regazzoni, F.: Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices. In: Bernstein, D.J., Lange, T. (eds.) AFRICACRYPT 2010. LNCS, vol. 6055, pp. 279–296. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  5. 5.
    Güneysu, T., Moradi, A.: Generic Side-Channel Countermeasures for Reconfigurable Devices. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 33–48. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  6. 6.
    Oswald, E., Mangard, S., Pramstaller, N., Rijmen, V.: A Side-Channel Analysis Resistant Description of the AES S-Box. In: Gilbert, H., Handschuh, H. (eds.) FSE 2005. LNCS, vol. 3557, pp. 413–423. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  7. 7.
    Itoh, K., Yajima, J., Takenaka, M., Torii, N.: DPA Countermeasures by Improving the Window Method. In: Kaliski, B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 303–317. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  8. 8.
    Herbst, C., Oswald, E., Mangard, S.: An AES Smart Card Implementation Resistant to Power Analysis Attacks. In: Zhou, J., Yung, M., Bao, F. (eds.) ACNS 2006. LNCS, vol. 3989, pp. 239–252. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  9. 9.
    Coron, J.S., Kizhvatov, I.: Analysis and Improvement of the Random Delay Countermeasure of CHES 2009. In: Mangard, S., Standaert, F.-X. (eds.) CHES 2010. LNCS, vol. 6225, pp. 95–109. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  10. 10.
    Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: Proceedings on Design, Automation and Test in Europe Conference and Exhibition 2004, vol. 1, pp. 246–251. IEEE Computer Society (February 2004)Google Scholar
  11. 11.
    Bucci, M., Luzzi, R., Guglielmo, M., Trifiletti, A.: A Countermeasure against Differential Power Analysis based on Random Delay Insertion. In: IEEE International Symposium on Circuits and Systems, ISCAS 2005, vol. 4, pp. 3547–3550. IEEE (May 2005)Google Scholar
  12. 12.
    Popp, T., Mangard, S.: Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 172–186. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  13. 13.
    Fischer, W., Gammel, B.M.: Masking at Gate Level in the Presence of Glitches. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 187–200. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  14. 14.
    Toprak, Z., Ienne, P., Paar, C.: Design of Low-Power DPA-Resistant Cryptographic Functional Units. In: Proceedings of the 1st ECRYPT Workshop on Cryptographic Advances in Secure Hardware, CRASH 2005 (2005)Google Scholar
  15. 15.
    Regazzoni, F., Badel, S., Eisenbarth, T., Groschdl, J., Poschmann, A., Toprak, Z., Macchetti, M., Pozzi, L., Paar, C., Leblebici, Y., Ienne, P.: Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. In: Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 2007) (July 2007)Google Scholar
  16. 16.
    Tiri, K., Verbauwhede, I.: Charge Recycling Sense Amplifier Based Logic: Securing Low Power Security IC’s against Differential Power Analysis. In: Proceeding of the 30th European Solid-State Circuits Conference, ESSCIRC 2004, pp. 179–182. IEEE (September 2004)Google Scholar
  17. 17.
    Suzuki, D., Saeki, M., Ichikawa, T.: Random Switching Logic: A Countermeasure against DPA based on Transition Probability. Techreport, Mitsubishi Electric Corporation, Mitsubishi Electric Engineering Company Limited, IACR ePrint (2004),
  18. 18.
    Chen, Z., Zhou, Y.: Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 242–254. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  19. 19.
    Tiri, K., Akmal, M., Verbauwhede, I.: A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards. In: Proceedings of the 29th European Solid-State Circuits Conference, ESSCIRC 2002, pp. 403–406 (2002)Google Scholar
  20. 20.
    Standaert, F.-X., Malkin, T.G., Yung, M.: A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks (extended version). Cryptology ePrint Archive, Report 2006/139 (2006)Google Scholar
  21. 21.
    Macé, F., Standaert, F.-X., Quisquater, J.-J.: Information Theoretic Evaluation of Side-Channel Resistant Logic Styles. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 427–442. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  22. 22.
    Tajalli, A., Vittoz, E., Leblebici, Y., Brauer, E.: Ultra low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept. In: 33rd European on Solid State Circuits Conference, ESSCIRC 2007, pp. 304–307 (2007)Google Scholar
  23. 23.
    Poschmann, A.Y.: Lightweight Cryptography: Cryptographic Engineering for a Pervasive World. Europäischer Universitäts-Verlag (2009)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Andreas Gornik
    • 1
  • Ivan Stoychev
    • 1
  • Jürgen Oehm
    • 1
  1. 1.Analogue Integrated Circuits Research GroupRuhr-Universität BochumBochumGermany

Personalised recommendations