Abstract
Hash algorithms are widely used for data integrity and authenticity. Chinese government recently published a standard hash algorithm, SM3, which is highly recommended for commercial applications. However, little research of SM3 implementation has been published. We find that the existing optimization techniques cannot be adopted to SM3 efficiently, due to the complex computation and strong data dependency. In this paper, we present our novel optimization techniques: shift initialization and SRL-based implementation. Based on the techniques, we propose two architectures: compact design and high-throughput design, both of which significantly improve the performance on FPGA. As far as we know, our work is the first one to evaluate SM3 hardware performance. The evaluation result suggests that SM3 with low area and high efficiency is suitable for hardware implementations, especially for those resource-limited platforms.
Keywords
- SM3
- hash algorithm
- FPGA
- optimization
- hardware performance evaluation
Download conference paper PDF
References
Chinese Commercial Cryptography Administration Office: Sepecification of SM3 Cryptographic Hash Function (2010) (in Chinese), http://www.oscca.gov.cn/UpFile/20101222141857786.pdf
HELION: Fast SHA-256 core for xilinx FPGA (2011), http://www.helion.com/
Chaves, R., Kuzmanov, G., Sousa, L., Vassiliadis, S.: Improving SHA-2 Hardware Implementations. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 298–310. Springer, Heidelberg (2006)
McEvoy, R.P., Crowe, F.M., Murphy, C.C., Marnane, W.P.: Optimisation of the SHA-2 Family of Hash Functions on FPGAs. In: IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI), pp. 317–322 (2006)
Chaves, R., Kuzmanov, G., Sousa, L., Vassiliadis, S.: Cost-Efficient SHA Hardware Accelerators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(8), 999–1008 (2008)
Macchetti, M., Dadda, L.: Quasi-Pipelined Hash Circuits. In: IEEE Symposium on Computer Arithmetic, pp. 222–229 (2005)
Michail, H.E., Kakarountas, A.P., Selimis, G.N., Goutis, C.E.: Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study. In: Paliouras, V., Vounckx, J., Verkest, D. (eds.) PATMOS 2005. LNCS, vol. 3728, pp. 591–600. Springer, Heidelberg (2005)
Lee, E.H., Lee, J.H., Park, I.H., Cho, K.R.: Implementation of High-Speed SHA-1 Architecture. IEICE Electronics Express 6(16), 1174–1179 (2009)
Sklavos, N., Koufopavlou, O.: Implementation of the SHA-2 Hash Family Standard Using FPGAs. The Journal of Supercomputing 31(3), 227–248 (2005)
Kakarountas, A.P., Michail, H., Milidonis, A., Goutis, C.E., Theodoridis, G.: High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications. The Journal of Supercomputing 37(2), 179–195 (2006)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Ma, Y., Xia, L., Lin, J., Jing, J., Liu, Z., Yu, X. (2012). Hardware Performance Optimization and Evaluation of SM3 Hash Algorithm on FPGA. In: Chim, T.W., Yuen, T.H. (eds) Information and Communications Security. ICICS 2012. Lecture Notes in Computer Science, vol 7618. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-34129-8_10
Download citation
DOI: https://doi.org/10.1007/978-3-642-34129-8_10
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-34128-1
Online ISBN: 978-3-642-34129-8
eBook Packages: Computer ScienceComputer Science (R0)
