Skip to main content

Advertisement

SpringerLink
Log in
Menu
Find a journal Publish with us
Search
Cart
Book cover

International Conference on Information and Communications Security

ICICS 2012: Information and Communications Security pp 105–118Cite as

  1. Home
  2. Information and Communications Security
  3. Conference paper
Hardware Performance Optimization and Evaluation of SM3 Hash Algorithm on FPGA

Hardware Performance Optimization and Evaluation of SM3 Hash Algorithm on FPGA

  • Yuan Ma18,19,
  • Luning Xia18,
  • Jingqiang Lin18,
  • Jiwu Jing18,
  • Zongbin Liu18 &
  • …
  • Xingjie Yu18,19 
  • Conference paper
  • 2252 Accesses

  • 6 Citations

Part of the Lecture Notes in Computer Science book series (LNSC,volume 7618)

Abstract

Hash algorithms are widely used for data integrity and authenticity. Chinese government recently published a standard hash algorithm, SM3, which is highly recommended for commercial applications. However, little research of SM3 implementation has been published. We find that the existing optimization techniques cannot be adopted to SM3 efficiently, due to the complex computation and strong data dependency. In this paper, we present our novel optimization techniques: shift initialization and SRL-based implementation. Based on the techniques, we propose two architectures: compact design and high-throughput design, both of which significantly improve the performance on FPGA. As far as we know, our work is the first one to evaluate SM3 hardware performance. The evaluation result suggests that SM3 with low area and high efficiency is suitable for hardware implementations, especially for those resource-limited platforms.

Keywords

  • SM3
  • hash algorithm
  • FPGA
  • optimization
  • hardware performance evaluation

Download conference paper PDF

References

  1. Chinese Commercial Cryptography Administration Office: Sepecification of SM3 Cryptographic Hash Function (2010) (in Chinese), http://www.oscca.gov.cn/UpFile/20101222141857786.pdf

  2. HELION: Fast SHA-256 core for xilinx FPGA (2011), http://www.helion.com/

  3. Chaves, R., Kuzmanov, G., Sousa, L., Vassiliadis, S.: Improving SHA-2 Hardware Implementations. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 298–310. Springer, Heidelberg (2006)

    CrossRef  Google Scholar 

  4. McEvoy, R.P., Crowe, F.M., Murphy, C.C., Marnane, W.P.: Optimisation of the SHA-2 Family of Hash Functions on FPGAs. In: IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI), pp. 317–322 (2006)

    Google Scholar 

  5. Chaves, R., Kuzmanov, G., Sousa, L., Vassiliadis, S.: Cost-Efficient SHA Hardware Accelerators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(8), 999–1008 (2008)

    CrossRef  Google Scholar 

  6. Macchetti, M., Dadda, L.: Quasi-Pipelined Hash Circuits. In: IEEE Symposium on Computer Arithmetic, pp. 222–229 (2005)

    Google Scholar 

  7. Michail, H.E., Kakarountas, A.P., Selimis, G.N., Goutis, C.E.: Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study. In: Paliouras, V., Vounckx, J., Verkest, D. (eds.) PATMOS 2005. LNCS, vol. 3728, pp. 591–600. Springer, Heidelberg (2005)

    CrossRef  Google Scholar 

  8. Lee, E.H., Lee, J.H., Park, I.H., Cho, K.R.: Implementation of High-Speed SHA-1 Architecture. IEICE Electronics Express 6(16), 1174–1179 (2009)

    CrossRef  Google Scholar 

  9. Sklavos, N., Koufopavlou, O.: Implementation of the SHA-2 Hash Family Standard Using FPGAs. The Journal of Supercomputing 31(3), 227–248 (2005)

    CrossRef  MATH  Google Scholar 

  10. Kakarountas, A.P., Michail, H., Milidonis, A., Goutis, C.E., Theodoridis, G.: High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications. The Journal of Supercomputing 37(2), 179–195 (2006)

    CrossRef  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. State Key Laboratory of Information Security, Institute of Information Engineering, CAS, Beijing, China

    Yuan Ma, Luning Xia, Jingqiang Lin, Jiwu Jing, Zongbin Liu & Xingjie Yu

  2. Graduate University of Chinese Academy of Sciences, Beijing, China

    Yuan Ma & Xingjie Yu

Authors
  1. Yuan Ma
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Luning Xia
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Jingqiang Lin
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Jiwu Jing
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Zongbin Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Xingjie Yu
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Department of Computer Science, The University of Hong Kong, Room 519, 5/F, Haking Building, Pokfulam Road, 852, Hong Kong, China

    Tat Wing Chim

  2. Department of Computer Science, The University of Hong Kong, Room 519, 5/F, Haking Wong Building, Pokfulam Road, 852, Hong Kong, China

    Tsz Hon Yuen

Rights and permissions

Reprints and Permissions

Copyright information

© 2012 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Ma, Y., Xia, L., Lin, J., Jing, J., Liu, Z., Yu, X. (2012). Hardware Performance Optimization and Evaluation of SM3 Hash Algorithm on FPGA. In: Chim, T.W., Yuen, T.H. (eds) Information and Communications Security. ICICS 2012. Lecture Notes in Computer Science, vol 7618. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-34129-8_10

Download citation

  • .RIS
  • .ENW
  • .BIB
  • DOI: https://doi.org/10.1007/978-3-642-34129-8_10

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-34128-1

  • Online ISBN: 978-3-642-34129-8

  • eBook Packages: Computer ScienceComputer Science (R0)

Share this paper

Anyone you share the following link with will be able to read this content:

Sorry, a shareable link is not currently available for this article.

Provided by the Springer Nature SharedIt content-sharing initiative

Search

Navigation

  • Find a journal
  • Publish with us

Discover content

  • Journals A-Z
  • Books A-Z

Publish with us

  • Publish your research
  • Open access publishing

Products and services

  • Our products
  • Librarians
  • Societies
  • Partners and advertisers

Our imprints

  • Springer
  • Nature Portfolio
  • BMC
  • Palgrave Macmillan
  • Apress
  • Your US state privacy rights
  • Accessibility statement
  • Terms and conditions
  • Privacy policy
  • Help and support

167.114.118.210

Not affiliated

Springer Nature

© 2023 Springer Nature