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Very Short Critical Path Implementation of AES with Direct Logic Gates

  • Kenta Nekado
  • Yasuyuki Nogami
  • Kengo Iokibe
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7631)

Abstract

A lot of improvements and optimizations for the hardware implementation of AES algorithm have been reported. These reports often use, instead of arithmetic operations in the AES original \(\mathbb{F}_{2^8}\), those in its isomorphic tower field \(\mathbb{F}_{((2^{2})^{2})^2}\) and \(\mathbb{F}_{(2^4)^2}\). This paper focuses on \(\mathbb{F}_{(2^4)^2}\) which provides higher–speed arithmetic operations than \(\mathbb{F}_{((2^{2})^{2})^2}\). In the case of adopting \(\mathbb{F}_{(2^4)^2}\), not only high–speed arithmetic operations in \(\mathbb{F}_{(2^4)^2}\) but also high–speed basis conversion matrices from the \(\mathbb{F}_{2^8}\) to \(\mathbb{F}_{(2^4)^2}\) should be used. Thus, this paper improves arithmetic operations in \(\mathbb{F}_{(2^4)^2}\) with Redundantly Represented Basis (RRB), and provides basis conversion matrices with More Miscellaneously Mixed Bases (MMMB).

Keywords

AES SubBytes MixColumns type–I optimal normal basis mixed bases 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Kenta Nekado
    • 1
  • Yasuyuki Nogami
    • 1
  • Kengo Iokibe
    • 1
  1. 1.Graduate School of Natural Science and TechnologyOkayama UniversityOkayama–cityJapan

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