Optimization of the Binary Adder Architectures Implemented in ASICs and FPGAs

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 195)

Abstract

In this paper both theoretical and experimental comparative performance analysis of several binary adder architectures is performed. Also, one modified carry-bypass technique for adder performance improvement is presented. When applying simple unit-gate theoretical model for area and delay estimation it has been shown that logarithmic delay architectures (carry-lookahead and prefix adders) are the fastest but the most hardware demanding. On the other hand, the implementations in modern Virtex-6 general purpose FPGAs witness that here presented carry-bypass technique is the best tradeoff for such devices in terms of area, speed and power consumption. Presented results can be considered as a valuable resource in the selection of the most appropriate adder topology that will be used to implement a given arithmetic operation in a specified technology.

Keywords

Binary adder architectures modified carry-bypass adder FPGA ASIC Power consumption 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Faculty of Electronic Engineering, Dept. of ElectronicsUniversity of NišNišSerbia

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