Meeting Real-Time Requirements with Multi-core Processors

  • Daniel Kästner
  • Marc Schlickling
  • Markus Pister
  • Christoph Cullmann
  • Gernot Gebhard
  • Reinhold Heckmann
  • Christian Ferdinand
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7613)


Many multi-core processors exhibit characteristics that make it difficult or even impossible to use them in safety-critical real-time systems. To prevent sporadic failures and late-stage integration problems, the hardware properties of the processor and its peripherals have to be checked for their real-time capability at an early project stage. Selecting a configuration which enables predictable performance is an important requirement to achieve compliance with current safety standards, e.g., ISO-26262, IEC-61508, EN-50128, or DO-178B.

For timing-predictable hardware configurations safe worst-case execution time bounds can be computed by static analysis tools. Combined with scheduling analysis at the system level the correct end-to-end timing can be guaranteed. This article gives an overview of hardware features leading to predictability problems, shows examples of predictability-oriented multi-core configurations, and describes a tool-based methodology to ensure the correct timing behavior.


Execution Time WCET Analysis Cache Replacement Policy Static Timing Analysis Private Cache 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Daniel Kästner
    • 1
  • Marc Schlickling
    • 1
  • Markus Pister
    • 1
  • Christoph Cullmann
    • 1
  • Gernot Gebhard
    • 1
  • Reinhold Heckmann
    • 1
  • Christian Ferdinand
    • 1
  1. 1.AbsInt GmbHSaarbrückenGermany

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