Abstract
In a software development cycle, it is often more than half of the development time that is dedicated to verification activities. Formal methods offer new possibilities for verification. In the specification phase, simulation or model-checking allow users to detect errors in models. In the implementation phase, analysis techniques, like static analysis, make the verification tasks more exhaustive and more automatic. In that context, we propose to take advantage of these methods to improve embedded software development processes based on the V-model.
Keywords
- Verification
- formal methods
- development process
- Model Based Engineering
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Fernandes Pires, A., Polacsek, T., Duprat, S. (2012). Formal Software Verification at Model and at Source Code Levels. In: Abelló, A., Bellatreche, L., Benatallah, B. (eds) Model and Data Engineering. MEDI 2012. Lecture Notes in Computer Science, vol 7602. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33609-6_16
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DOI: https://doi.org/10.1007/978-3-642-33609-6_16
Publisher Name: Springer, Berlin, Heidelberg
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