3D Hardware Canaries

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7428)


3D integration is a promising advanced manufacturing process offering a variety of new hardware security protection opportunities. This paper presents a way of securing 3D ICs using Hamiltonian paths as hardware integrity verification sensors. As 3D integration consists in the stacking of many metal layers, one can consider surrounding a security-sensitive circuit part by a wire cage.

After exploring and comparing different cage construction strategies (and reporting preliminary implementation results on silicon), we introduce a ”hardware canary”. The canary is a spatially distributed chain of functions F i positioned at the vertices of a 3D cage surrounding a protected circuit. A correct answer (F n  ∘ … ∘ F 1)(m) to a challenge m attests the canary’s integrity.


Metal Layer Hamiltonian Cycle Hamiltonian Path Black Vertex White Vertex 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© International Association for Cryptologic Research 2012

Authors and Affiliations

  1. 1.Département d’informatiqueÉcole normale supérieureFrance
  2. 2.Altis SemiconductorFrance
  3. 3.Sorbonne Universités – Université Paris iiFrance
  4. 4.Secure-ICFrance
  5. 5.Département Communications et ElectroniqueTélécom-ParisTechFrance

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