Abstract
Instruction Scheduling as a compiler optimization is a very powerful technique to enable instruction level parallelism for many types of modern architectures. Instruction Scheduling can be used for making best fill of the micro-architecture pipeline (by minimizing the number of pipeline stalls) and is also of critical importance for keeping as busy as possible the multiple execution units for the architectures with parallel execution sets (like VLIW, EPIC or VLES architectures). This paper will present a set of improvements that can be brought to an instruction scheduling technique implemented in a real compiler for a VLIW architecture, where both pipeline aspects and multiple execution units are exploited. The improvements are based on practical and theoretical observations. They include a possible false-WAW dependence improvement, another improvement by considering inter-block latencies and also some improvements about hyper-block scheduling and IF-conversion integration with instruction scheduling.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Ditu, B., Tapus, N.: Improvements of Instruction Scheduling. In: Proceedings of 18th Conference on Control Systems and Computer Science, pp. 545–552 (2011)
Muchnick, S.S.: Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers (1997)
Gibbons, P.A., Muchnick, S.S.: Efficient Instruction Scheduling for a Pipelined Processor. In: Proceedings of the SIGPLAN 1986 Symposium on Compiler Construction. SIGPLAN Notices, vol. 21(7), pp. 11–16 (1986)
Fisher, J.A.: Trace Scheduling: A technique for Global Microcode Compaction. IEEE Trans. on Comps. C-30(7), 478–490 (1981)
Nicolau, A.: A Fine-Grain Parallelizing Compiler, Technical Report TR-86-792, Department of Computer Science, Cornell Univ., Ithaca, NY (1986)
Codina, J.M., Llosa, J., Gonzalez, A.: A Comparative Study of Modulo Scheduling Techniques. In: ICS 2002 (2002)
Rau, B.R.: Iterative Modulo Scheduling. An Algorithm for Software Pipelining Loops, MICRO 27, 63–74 (1994)
Aho, A.V., Lam, M.S., Sethi, R., Ullman, J.D.: Compilers, Principles, Techniques, and Tools. Addison-Wesley (2007)
Chakrapani, L.N., Gyllenhaal, J., Hwu, W.W., Mahlke, S.A., Palem, K.V., Rabbah, R.M.: An infrastructure for research in instruction-level parallelism. In: Proceedings of the 17th International Workshop on Languages and Compilers for High Performance Computing (2005)
Malik, A.M., Russell, T., Chase, M., van Beek, P.: Learning heuristics for basic block instruction scheduling. Journal of Heuristics (2006)
Malik, A.M., McInnes, J., van Beek, P.: Optimal basic block instruction scheduling for multiple-issue processors using constraint programming. In: Proceedings of the 18th IEEE International Conference on Tools with Artificial Intelligence (2006)
Malik, A.M., Russell, T., Chase, M., van Beek, P.: Optimal superblock instruction scheduling for multiple-issue processors using constraint programming. School of Computer Science, University of Waterloo (2006)
Russle, T., Malik, A.M., Chase, M., van Beek, P.: Learning Heuristics for Superblock Instruction Scheduling. School of Computer Science, University of Waterloo (2006)
Memik, G., Reinman, G., Mangione-Smith, W.H.: Precise Instruction Scheduling. Journal of Instruction-Level Parallelism 7 (2005)
Rangan, R., Vachharajani, N., Vachharajani, M., August, D.I.: Decoupled software pipelining with the synchronization array. In: Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (2004)
Winkel, S.: Exploring the performance potential of Itanium processors with ILP-based scheduling. In: Proceedings of the International Symposium on Code Generation and Optimization. IEEE Computer Society (2004)
Parikh, A., Kim, S., Kandemir, M., Vijaykrishnan, N., Irwin, M.J.: Instruction Scheduling for Low Power. Department of Computer Science and Engineering, The Pennsylvania State University (2003)
Zane, A., Chircu, M., Costinescu, S., Palanciuc, V., Badea, D.: Integrated Instruction Scheduling and If-Conversion. In: International Signal Processing Conference (2003)
Ditu, B.: IF-conversion controlled by Instruction Scheduling. In: Proceedings of 15th Conference of Control Systems and Computer Science, pp. 706–711 (2005)
Ditu, B.: Automatic Optimizations based on Profile Information. In: Proceedings of Embedded World Conference (2010)
Ghica, L., Ditu, B., Tapus, N.: A Study of Architecture Modeling in the Context of Development Tools Chain. In: Proceedings of 18th Conference on Control Systems and Computer Science, pp. 308–313 (2011)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Ditu, B., Tapus, N. (2013). Improvements of Instruction Scheduling. In: Dumitrache, L. (eds) Advances in Intelligent Control Systems and Computer Science. Advances in Intelligent Systems and Computing, vol 187. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-32548-9_29
Download citation
DOI: https://doi.org/10.1007/978-3-642-32548-9_29
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-32547-2
Online ISBN: 978-3-642-32548-9
eBook Packages: EngineeringEngineering (R0)